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公开(公告)号：US11755099B2
公开(公告)日：2023-09-12
申请号：US17852066
申请日：2022-06-28
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
CPC classification number: G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3466 , G06F11/3409 , G06F11/3452 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/00 , Y02D30/50
Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.
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公开(公告)号：US20190332158A1
公开(公告)日：2019-10-31
申请号：US16508916
申请日：2019-07-11
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
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公开(公告)号：US09501135B2
公开(公告)日：2016-11-22
申请号：US14169955
申请日：2014-01-31
Applicant: INTEL CORPORATION
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
CPC classification number: G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能度量好时，程序代码的执行可以从第一处理核心切换到第二处理核心。
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公开(公告)号：US10437319B2
公开(公告)日：2019-10-08
申请号：US14986678
申请日：2016-01-02
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
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公开(公告)号：US09817644B2
公开(公告)日：2017-11-14
申请号：US14867950
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Mauricio Breternitz, Jr. , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Craig B. Zilles
CPC classification number: G06F8/443 , G06F8/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30116 , G06F9/3842 , G06F9/3857 , G06F9/466 , G06F11/3672 , G06F11/3688
Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
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Patent Agency Ranking
公开(公告)号：US20140223166A1
公开(公告)日：2014-08-07
申请号：US14169955
申请日：2014-01-31
Applicant: INTEL CORPORATION
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC: G06F9/445
CPC classification number: G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。
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公开(公告)号：US10534424B2
公开(公告)日：2020-01-14
申请号：US14986676
申请日：2016-01-02
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
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8.发明授权Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region 有权用于提供原子区域中的条件提交的决策机制的装置，方法和系统公开(公告)号：US09146844B2
公开(公告)日：2015-09-29
申请号：US13893238
申请日：2013-05-13
Applicant: INTEL CORPORATION
Inventor： Mauricio Breternitz , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Craig B. Zilles
CPC classification number: G06F8/443 , G06F8/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30116 , G06F9/3842 , G06F9/3857 , G06F9/466 , G06F11/3672 , G06F11/3688
Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
Abstract translation: 本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。
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公开(公告)号：US20220326756A1
公开(公告)日：2022-10-13
申请号：US17852066
申请日：2022-06-28
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core
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公开(公告)号：US10437318B2
公开(公告)日：2019-10-08
申请号：US14986677
申请日：2016-01-02
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
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