公开(公告)号：US20190355826A1

公开(公告)日：2019-11-21

申请号：US16474874

申请日：2017-04-11

Applicant: INTEL CORPORATION

Inventor： UYGAR E. AVCI ,  DANIEL H. MORRIS ,  IAN A. YOUNG

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including a channel region, a gate dielectric between the gate electrode and the channel region, a first layer between the gate dielectric and the gate electrode, the first layer comprising temperature compensation material. In addition, the integrate circuit includes a source region adjacent to the channel region, a source metal contact on the source region, a drain region adjacent to the channel region, and a drain metal contact on the drain region. The temperature compensation material has a temperature dependent band structure, work-function, or polarization that dynamically adjusts the threshold voltage of the transistor in response to increased operating temperature to maintain the off-state current Ioff stable or otherwise within an acceptable tolerance. The temperature compensation material may be used in conjunction with a work function material to help provide desired performance at lower or non-elevated temperatures.

公开(公告)号：US20190181249A1

公开(公告)日：2019-06-13

申请号：US16306540

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： SASIKANTH MANIPATRUNI ,  ANURAG CHAUDHRY ,  DMITRI E. NIKONOV ,  JASMEET S. CHAWLA ,  CHRISTOPHER J. WIEGAND ,  KANWALJIT SINGH ,  UYGAR E. AVCI ,  IAN A. YOUNG

IPC: H01L29/66 ,  H01L29/47 ,  H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/06 ,  H01L21/285

Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.

公开(公告)号：US20170287555A1

公开(公告)日：2017-10-05

申请号：US15088080

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： HUICHU LIU ,  SASIKANTH MANIPATRUNI ,  IAN A. YOUNG ,  TANAY KARNIK ,  DANIEL H. MORRIS ,  KAUSHIK VAIDYANATHAN

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/56 ,  G11C2213/79 ,  G11C2213/82 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An apparatus is described that includes a resistive random access memory cell having a word line that is to receive a narrowed word line signal that limits an amount of time that an access transistor is on so as to limit the cell's high resistive state and/or the cell's low resistive state. Another apparatus is described that includes a resistive random access memory cell having SL and BL lines that are to receive respective signals having different voltage amplitudes to reduce source degeneration effects of the resistive random access memory cell's access transistor. Another apparatus is described that includes a resistive random access memory cell having a storage cell comprising a bottom-side OEL layer. Another apparatus is described that includes a resistive random access memory cell having a storage cell within a metal layer that resides between a pair of other metal layers where parallel SL and BL lines of the resistive random access memory cell respectively reside.

公开(公告)号：US20160203865A1

公开(公告)日：2016-07-14

申请号：US14913676

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： SASIKANTH MANIPATRUNI ,  DMITRI E. NIKONOV ,  IAN A. YOUNG

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C2213/79 ,  G11C2213/82

Abstract: Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.

Abstract translation: 描述了一种装置，包括：第一选择线; 第二选择线; 有点线 第一位单元，包括电阻存储元件和晶体管，所述第一位单元耦合到所述第一选择线和所述位线; 具有耦合到第一选择线的输入和耦合到第二选择线的输出的缓冲器; 以及包括电阻存储元件和晶体管的第二位单元，所述第二位单元耦合到所述第二选择线和所述位线。 描述了一种磁性随机存取存储器（MRAM），包括：多行，每行包括：多个位单元，每个位单元具有耦合到晶体管的MTJ器件; 以及多个缓冲器，每个缓冲器用于缓冲所述多个位单元中的一组位单元的选择线信号; 和多个位线，每行在该行中的多个位单元之中共享单个位线。

公开(公告)号：US20160173100A1

公开(公告)日：2016-06-16

申请号：US14906025

申请日：2013-09-30

Applicant: Intel Corporation

Inventor： DMITRI E. NIKONOV ,  SASIKANTH MANIPATRUNI ,  MICHAEL KISHINEVSKY ,  IAN A. YOUNG

IPC: H03K19/16 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: H03K19/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08 ,  H03K19/18

Abstract: An embodiment includes a C-element logic gate implemented as a spin logic device that provides a compact and low-power implementation of asynchronous logic by implementing a C-element with spintronic technology. An embodiment includes a first nanopillar including a first contact and a first fixed magnetic layer; a second nanopillar including a second contact and a second fixed magnetic layer; and a third nanopillar including a third contact, a tunnel barrier, and a third fixed magnetic layer; wherein (a) the first, second, and third nanopillars are all formed over a free magnetic layer, and (b) the third fixed magnetic layer, the tunnel barrier, and the free magnetic layer form a magnetic tunnel junction (MTJ). Other embodiments are described herein.

Abstract translation: 实施例包括被实现为自旋逻辑器件的C元件逻辑门，其通过使用自旋电子技术实现C元件来提供异步逻辑的紧凑和低功率实施。 一个实施例包括第一纳米柱，其包括第一接触和第一固定磁性层; 包括第二接触和第二固定磁性层的第二纳米柱; 以及包括第三接触件，隧道势垒和第三固定磁性层的第三纳米柱; 其中（a）第一，第二和第三纳米锥都形成在自由磁性层上，并且（b）第三固定磁性层，隧道势垒和自由磁性层形成磁性隧道结（MTJ）。 本文描述了其它实施例。