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公开(公告)号:US12020068B2
公开(公告)日:2024-06-25
申请号:US17022332
申请日:2020-09-16
Applicant: Intel Corporation
Inventor: Chris MacNamara , Amruta Misra , John Browne
IPC: G06F9/48 , G06F9/455 , G06F12/0875 , G06F13/20
CPC classification number: G06F9/4893 , G06F9/45558 , G06F12/0875 , G06F13/20 , G06F2212/1016
Abstract: Methods to automatically prioritize input/output (I/O) for Network Function Virtualization (NFV) workloads at platform overload and associated apparatus and mechanisms. During lab or runtime workload operations, various platform telemetry data are collected and analyzed to determine whether a current workload is uncore-sensitive—that is, sensitive to operations involving utilization of the uncore circuitry such as I/O-related operations, memory bandwidth utilization, LLC utilization, network traffic, core-to-core traffic etc. For uncore sensitive workloads, upon detection of a platform overload condition such as a thermal load approaching a TDP limit, the uncore circuitry is prioritized over the core circuitry such that the frequency of the core is reduced first. A closed-loop feedback mechanism is used to adjust the frequencies of the core and uncore under various workload conditions. The mechanism enables I/O throughput to be maintained for NFV workloads, while reducing the processor thermal load.
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公开(公告)号:US20210117191A1
公开(公告)日:2021-04-22
申请号:US17133305
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Andrew Cunningham , Patrick Fleming , Naveen Lakkakula , Richard Guerin , Charitra Sankar , Stephen Doyle , Ralph Castro , John Browne
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.
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公开(公告)号:US20190044860A1
公开(公告)日:2019-02-07
申请号:US16011103
申请日:2018-06-18
Applicant: Intel Corporation
Inventor: Chris MacNamara , John Browne , Tomasz Kantecki , Ciara Loftus , John Barry , Patrick Connor , Patrick Fleming
IPC: H04L12/801 , H04L12/861 , H04L12/841
Abstract: Technologies for providing adaptive polling of packet queues include a compute device. The compute device includes a network interface controller and a compute engine that includes a set of cores and a memory that includes a queue to store packets received by the network interface controller. The compute engine is configured to determine a predicted time period for the queue to receive packets without overflowing, execute, during the time period and with a core that is assigned to periodically poll the queue for packets, a workload, and poll, with the assigned core, the queue to remove the packets from the queue. Other embodiments are also described and claimed.
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公开(公告)号:US20190042310A1
公开(公告)日:2019-02-07
申请号:US15951650
申请日:2018-04-12
Applicant: Intel Corporation
Inventor: John Browne , Chris MacNamara , Tomasz Kantecki , Peter McCarthy , Ma Liang , Mairtin O'Loingsigh , Rory Sexton , John Griffin , Nemanja Marjanovic , David Hunt
IPC: G06F9/48 , G06F1/32 , H04L12/851
Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.
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公开(公告)号:US11800439B2
公开(公告)日:2023-10-24
申请号:US18067033
申请日:2022-12-16
Applicant: Intel Corporation
Inventor: Shahrnaz Azizi , Biljana Badic , John Browne , Dave Cavalcanti , Hyung-Nam Choi , Thorsten Clevorn , Ajay Gupta , Maruti Gupta Hyde , Ralph Hasholzner , Nageen Himayat , Simon Hunt , Ingolf Karls , Thomas Kenney , Yiting Liao , Christopher MacNamara , Marta Martinez Tarradell , Markus Dominik Mueck , Venkatesan Nallampatti Ekambaram , Niall Power , Bernhard Raaf , Reinhold Schneider , Ashish Singh , Sarabjot Singh , Srikathyayani Srikanteswara , Shilpa Talwar , Feng Xue , Zhibin Yu , Robert Zaus , Stefan Franz , Uwe Kliemann , Christian Drewes , Juergen Kreuchauf
CPC classification number: H04W48/16 , H04W4/029 , H04W24/08 , H04W48/10 , H04W68/005 , H04W92/045
Abstract: A wireless communication device includes a processor configured to select an offload processing task for performance by an edge computing device; cause a baseband modem to establish a direct wireless connection between the wireless communication device and the edge computing device; cause the baseband modem to send first data to the edge computing device via the direct wireless connection; and receive second data from the edge computing device, wherein the second data comprise a result of the offload processing task performed on the first data. The edge computing device includes a processor configured to receive, from a user device, offloaded data to be processed according to an offload processing task; execute the offload processing task on the offloaded data; and cause the radio via the interface to wirelessly send a result of the executed offload processing task via a direct wireless connection with the user device.
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公开(公告)号:US20220391110A1
公开(公告)日:2022-12-08
申请号:US17865594
申请日:2022-07-15
Applicant: Intel Corporation
Inventor: Fei Wang , John Browne , Laurent Coquerel
IPC: G06F3/06
Abstract: An accelerator device may access an input data chunk to be compressed by the accelerator device. The accelerator device may access an entropy value for the input data chunk. The accelerator device may compress the input data chunk or return an indication that the input data chunk will not be compressed based on the entropy value and an entropy threshold.
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公开(公告)号:US11388074B2
公开(公告)日:2022-07-12
申请号:US16381237
申请日:2019-04-11
Applicant: Intel Corporation
Inventor: Peter McCarthy , Chris MacNamara , John Browne , Liang J. Ma , Liam Day
IPC: G06F1/32 , H04L43/00 , H04L43/10 , H04L41/0833 , H04L43/022 , H04L43/16 , G06F1/3209
Abstract: Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.
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公开(公告)号:US20250117318A1
公开(公告)日:2025-04-10
申请号:US18987168
申请日:2024-12-19
Applicant: Intel Corporation
Inventor: Sunku Ranganath , John Browne , Hassnaa Moustafa , Mandar Chincholkar , Amar Srivastava
IPC: G06F12/02
Abstract: Memory management for wireless networks is described. A method, includes accessing an operational parameter for a network slice of a wireless network, determining a first memory region of a plurality of memory regions in the memory pool based on the operational parameter, and encoding configuration information to allocate the first memory region to the network slice. Other embodiments are described and claimed.
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公开(公告)号:US12127103B2
公开(公告)日:2024-10-22
申请号:US18462444
申请日:2023-09-07
Applicant: Intel Corporation
Inventor: Shahrnaz Azizi , Biljana Badic , John Browne , Dave Cavalcanti , Hyung-Nam Choi , Thorsten Clevorn , Ajay Gupta , Maruti Gupta Hyde , Ralph Hasholzner , Nageen Himayat , Simon Hunt , Ingolf Karls , Thomas Kenney , Yiting Liao , Christopher MacNamara , Marta Martinez Tarradell , Markus Dominik Mueck , Venkatesan Nallampatti Ekambaram , Niall Power , Bernhard Raaf , Reinhold Schneider , Ashish Singh , Sarabjot Singh , Srikathyayani Srikanteswara , Shilpa Talwar , Feng Xue , Zhibin Yu , Robert Zaus , Stefan Franz , Uwe Kliemann , Christian Drewes , Juergen Kreuchauf
CPC classification number: H04W48/16 , H04W4/029 , H04W24/08 , H04W48/10 , H04W68/005 , H04W92/045
Abstract: A circuit arrangement includes a preprocessing circuit configured to obtain context information related to a user location, a learning circuit configured to determine a predicted user movement based on context information related to a user location to obtain a predicted route and to determine predicted radio conditions along the predicted route, and a decision circuit configured to, based on the predicted radio conditions, identify one or more first areas expected to have a first type of radio conditions and one or more second areas expected to have a second type of radio conditions different from the first type of radio conditions and to control radio activity while traveling on the predicted route according to the one or more first areas and the one or more second areas.
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公开(公告)号:US11630693B2
公开(公告)日:2023-04-18
申请号:US15951650
申请日:2018-04-12
Applicant: Intel Corporation
Inventor: John Browne , Chris MacNamara , Tomasz Kantecki , Peter McCarthy , Liang Ma , Mairtin O'Loingsigh , Rory Sexton , John Griffin , Nemanja Marjanovic , David Hunt
IPC: G06F9/46 , G06F9/48 , H04L47/24 , G06F1/329 , H04L9/40 , H04L47/6275 , G06F1/3209 , G06F1/3296 , G06F1/3234 , H04L47/625 , G06F9/50 , G06F21/60
Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.
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