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    PLANAR HETEROGENEOUS DEVICE
    1.
    发明申请
    PLANAR HETEROGENEOUS DEVICE 审中-公开
    平面异构器件

    公开(公告)号：US20160247882A1

    公开(公告)日：2016-08-25

    申请号：US15026271

    申请日：2013-12-18

    Applicant: INTEL CORPORATION

    Inventor： KIMIN JUN ,  PATRICK MORROW

    IPC: H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L27/12 ,  H01L29/267 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L29/22

    CPC classification number: H01L29/1054 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/8258 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/78

    Abstract: In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.

    Abstract translation: 在一个实施例中，在第一半导体层的顶部上转移第二半导体层（例如，使用层转移技术）。 将第二层图案化成所需的孔。 在井之间，第一层被暴露。 将暴露的第一层外延生长至转移的第二层的水平，以完成包括S1和S2的平面异质衬底。 可以利用异质材料，使得例如由III-V或IV材料中的一种形成的P沟道器件与由III-V或IV族材料之一形成的N沟道器件共面。 由于第二层被转移到第一层上，本实施例不需要晶格参数的顺应性。 此外，没有（或少量）缓冲和/或异质外延。 本文描述了其它实施例。

    BACKSIDE CONTACT RESISTANCE REDUCTION FOR SEMICONDUCTOR DEVICES WITH METALLIZATION ON BOTH SIDES
    2.
    发明申请
    BACKSIDE CONTACT RESISTANCE REDUCTION FOR SEMICONDUCTOR DEVICES WITH METALLIZATION ON BOTH SIDES 审中-公开

    公开(公告)号：US20190157310A1

    公开(公告)日：2019-05-23

    申请号：US16306295

    申请日：2016-07-01

    Applicant: INTEL CORPORATION

    Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  CHANDRA S. MOHAPATRA ,  MAURO J. KOBRINSKY ,  PATRICK MORROW

    IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/775

    Abstract: Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material. Other embodiments may be described and/or disclosed.

    HETEROGENEOUS LAYER DEVICE
    3.
    发明申请
    HETEROGENEOUS LAYER DEVICE 审中-公开
    异构层设备

    公开(公告)号：US20160247887A1

    公开(公告)日：2016-08-25

    申请号：US15026614

    申请日：2013-12-18

    Applicant: INTEL CORPORATION

    Inventor： KIMIN JUN ,  PATRICK MORROW

    IPC: H01L29/267 ,  H01L29/417 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06

    CPC classification number: H01L29/267 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/413 ,  H01L29/4175 ,  H01L29/66439 ,  H01L29/775

    Abstract: An embodiment includes an apparatus comprising: an N layer comprising an NMOS device having a N channel, source, and drain that are all intersected by a first horizontal axis that is parallel to a substrate; a P layer comprising a PMOS device having a P channel, source, and drain that are all intersected by a second horizontal axis that is parallel to the substrate; a first gate, corresponding to the N channel, which intersects the second horizontal axis; and a second gate, corresponding to the P channel, which intersects the first horizontal axis. Other embodiments are described herein.

    Abstract translation: 实施例包括一种装置，包括：N层，包括具有N沟道，源极和漏极的NMOS器件，所述N沟道，源极和漏极都与平行于衬底的第一水平轴相交; P层，包括具有P沟道，源极和漏极的PMOS器件，所述PMOS器件都与平行于衬底的第二水平轴相交; 对应于与第二水平轴相交的N通道的第一门; 以及与P沟道相对应的与第一水平轴相交的第二门。 本文描述了其它实施例。

    BACK SIDE PROCESSING OF INTEGRATED CIRCUIT STRUCTURES TO FORM INSULATION STRUCTURE BETWEEN ADJACENT TRANSISTOR STRUCTURES
    4.
    发明申请
    BACK SIDE PROCESSING OF INTEGRATED CIRCUIT STRUCTURES TO FORM INSULATION STRUCTURE BETWEEN ADJACENT TRANSISTOR STRUCTURES 审中-公开

    公开(公告)号：US20190341297A1

    公开(公告)日：2019-11-07

    申请号：US16473902

    申请日：2017-03-30

    Applicant: INTEL CORPORATION

    Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  PATRICK MORROW

    IPC: H01L21/762 ,  H01L27/12 ,  H01L21/8234

    Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

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