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公开(公告)号：US20160246342A1
公开(公告)日：2016-08-25
申请号：US15025871
申请日：2013-12-18
Applicant: INTEL CORPORATION
Inventor： Ramnarayanan MUTHUKARUPPAN , Pradipta PATRA , Gaurav GOEL , Uday Bhaskar KADALI
Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
Abstract translation: 描述了具有自适应增益的电压调节器，其包括：可由数字总线控制的多个功率门晶体管，所述多个功率栅极晶体管可操作以向负载提供第一电源，以及接收第二电源 作为输入; 模数转换器（ADC），用于接收第一电源并产生代表第一电源的数字输出; 以及控制器，用于接收代表第一电源的数字输出并产生用于控制多个功率门晶体管的数字总线，使得多个功率栅极晶体管的传递函数在工作范围内基本上是线性的。
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Patent Agency Ranking
公开(公告)号：US20180364780A1
公开(公告)日：2018-12-20
申请号：US16062093
申请日：2016-11-23
Applicant: INTEL CORPORATION
Abstract: A configuration interface bus may be coupled to components of a physical layer (PHY) device. A configuration controller may be coupled with the configuration interface bus and may receive an input signal representing a power state of the PHY device. The configuration controller may further identify a set of instructions that correspond to the input signal and may transmit configuration data via the configuration interface bus to one or more of the components of the PHY device in response to an execution of the set of instructions. The operation of the one or more components of the PHY device may be based on the configuration data.
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公开(公告)号：US20180267480A1
公开(公告)日：2018-09-20
申请号：US15462732
申请日：2017-03-17
Applicant: Intel Corporation
Inventor： Tarun MAHAJAN , Dheeraj SHETTY , Ramnarayanan MUTHUKARUPPAN
CPC classification number: G04F10/005 , G05F1/561 , G06F1/06 , H03M1/00 , H03M1/12 , H03M2201/4233
Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.
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公开(公告)号：US20190220074A1
公开(公告)日：2019-07-18
申请号：US16359810
申请日：2019-03-20
Applicant: Intel Corporation
Inventor： Ramnarayanan MUTHUKARUPPAN , Pradipta PATRA , Gaurav GOEL , Uday Bhaskar KADALI
Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
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公开(公告)号：US20190212704A1
公开(公告)日：2019-07-11
申请号：US16242953
申请日：2019-01-08
Applicant: Intel Corporation
Inventor： Tarun MAHAJAN , Dheeraj SHETTY , Ramnarayanan MUTHUKARUPPAN
Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.
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6.发明申请MULTIPLE VOLTAGE IDENTIFICATION (VID) POWER ARCHITECTURE, A DIGITAL SYNTHESIZABLE LOW DROPOUT REGULATOR, AND APPARATUS FOR IMPROVING RELIABILITY OF POWER GATES 审中-公开多电压识别（VID）电源结构，数字合成低压差稳压器，以及改善电网可靠性的设备公开(公告)号：US20170031411A1
公开(公告)日：2017-02-02
申请号：US15292067
申请日：2016-10-12
Applicant: Intel Corporation
Inventor： Ramnarayanan MUTHUKARUPPAN , Harish K. KRISHNAMURTHY , Mohit VERMA , Pradipta PATRA , Uday Bhaskar KADALI
IPC: G06F1/32
CPC classification number: G06F1/32 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/152 , Y02D10/172
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
Abstract translation: 描述了一种装置，包括：第一和第二处理核; 以及PCU，其可操作用于：为所述装置外部的所述离线外调节器产生第一VID，所述第一VID导致所述第一处理核心的第一电源; 并产生与第一VID不同的第二VID，第二VID导致用于第二处理核的第二电源。 描述了一种装置，包括：由数字总线控制的多个功率门晶体管，所述多个功率栅晶体管可操作以向处理核提供第一电源，并接收作为输入的第二电源; ADC，用于接收第一电源并产生代表第一电源的数字输出; 以及控制器，用于接收数字输出代表并产生用于控制多个功率门晶体管的数字总线。
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