公开(公告)号：US20190243577A1

公开(公告)日：2019-08-08

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  David B. CARLTON ,  Mark Anthony GOLEZ ,  Xin GUO ,  Aliasgar S. MADRASWALA ,  Sagar S. SIDHPURA ,  Sagar UPADHYAY ,  Neelesh VEMULA ,  Yogesh B. WAKCHAURE ,  Ye ZHANG

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

公开(公告)号：US20210249092A1

公开(公告)日：2021-08-12

申请号：US16786948

申请日：2020-02-10

Applicant: INTEL CORPORATION

Inventor： Tarek Ahmed AMEEN BESHARI ,  Pranav CHAVA ,  Shantanu R. RAJWADE ,  Sagar UPADHYAY

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.

公开(公告)号：US20210383880A1

公开(公告)日：2021-12-09

申请号：US16895890

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Pranav CHAVA ,  Aliasgar S. MADRASWALA ,  Sagar UPADHYAY ,  Bhaskar VENKATARAMAIAH

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C7/22

Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

公开(公告)号：US20190006016A1

公开(公告)日：2019-01-03

申请号：US15638260

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Shantanu R. RAJWADE ,  Aliasgar S. MADRASWALA ,  Uday CHANDRASEKHAR ,  Purval S. SULE ,  Sagar UPADHYAY

IPC: G11C16/34 ,  G11C16/10 ,  G11C8/06 ,  G11C8/10 ,  G06F11/14

Abstract: A programming of a memory device configurable to reach a plurality of voltage levels is initiated. For each voltage level to be reached, a checkpoint is set up within a sequence of program pulses applied for the programming of the memory device, to determine whether a plurality of memory cells of the memory device have reached the voltage level. The programming of the memory device is aborted, in response to determining at the checkpoint that the plurality of memory cells have not reached the voltage level.