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公开(公告)号：US20220084606A1
公开(公告)日：2022-03-17
申请号：US17023094
申请日：2020-09-16
申请人： Intel Corporation
摘要： A method is described. The method includes programming a column of flash storage cells in a direction along the column in which a parasitic transistor that resides between a cell being programmed and an immediately next cell to be programmed has lower resistivity as compared to a corresponding parasitic transistor that exists if the programming were to be performed in an opposite direction along the column.
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公开(公告)号：US20190227751A1
公开(公告)日：2019-07-25
申请号：US16370743
申请日：2019-03-29
申请人： Intel Corporation
摘要： A memory device is designed to store data in multilevel storage cells (MLC storage cells). The memory device includes a controller that dynamically writes data to the storage cells according to a first MLC density or a second MLC density. The second density is less dense than the first density. For example, the controller can determine to use the first density when there is sufficient write bandwidth to program the storage cells at the first density. When the write throughput increases, the controller can program the same MLC storage cells at the second density instead of the first density, using the same program process and voltage.
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3.发明申请公开(公告)号：US20210304820A1
公开(公告)日：2021-09-30
申请号：US16828843
申请日：2020-03-24
申请人： Intel Corporation
摘要： A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.
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公开(公告)号：US20210193200A1
公开(公告)日：2021-06-24
申请号：US17195579
申请日：2021-03-08
申请人： Intel Corporation
摘要： Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines. In some examples, identification of open or shorted bit lines can be used to identify read operations involving those open or shorted bit lines as weak in connection with performing soft bit read correction.
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公开(公告)号：US20200090743A1
公开(公告)日：2020-03-19
申请号：US16593868
申请日：2019-10-04
申请人： Intel Corporation
发明人： Aliasgar S. MADRASWALA , Bharat M. PATHAK , Binh N. NGO , Naveen VITTAL PRABHU , Karthikeyan RAMAMURTHI , Pranav KALAVADE
摘要： A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.
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公开(公告)号：US20190043589A1
公开(公告)日：2019-02-07
申请号：US15948556
申请日：2018-04-09
申请人： Intel Corporation
发明人： Zion S. KWOK , Pranav KALAVADE , Ravi H. MOTWANI
摘要： One-sided soft reads can enable improved error-correction over regular reads without significantly increasing the latency for reads. In one example, a flash storage device includes an array of storage cells and a controller to access the array of storage cells. The controller is to perform at least one read of a storage cell to cause a read strobe to be applied at an expected read reference voltage and also cause one or more additional read strobes to be applied of the at voltages on only one side of the expected read reference voltage (e.g., which in some cases involves applying the additional one or more read strobes at a voltage with a slightly lower or higher magnitude than the magnitude of the expected read reference voltage). The controller can then provide a logic value and one or more bits indicating confidence or reliability of the logic value's accuracy based on an electrical response of the storage cell to the read strobe and the one or more additional read strobes.
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公开(公告)号：US20180122487A1
公开(公告)日：2018-05-03
申请号：US15715980
申请日：2017-09-26
申请人： Intel Corporation
发明人： Shantanu R. RAJWADE , Pranav KALAVADE , Neal R. MIELKE , Krishna K. PARAT , Shyam Sunder RAGHUNATHAN
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
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公开(公告)号：US20210074338A1
公开(公告)日：2021-03-11
申请号：US16562745
申请日：2019-09-06
申请人： Intel Corporation
摘要： Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.
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公开(公告)号：US20190287627A1
公开(公告)日：2019-09-19
申请号：US16412269
申请日：2019-05-14
申请人： Intel Corporation
发明人： Krishna K. PARAT , Pranav KALAVADE , Koichi Kawai , Akira Goda
摘要： Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify
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公开(公告)号：US20190103159A1
公开(公告)日：2019-04-04
申请号：US15720492
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： Ali KHAKIFIROOZ , Rohit S. SHENOY , Pranav KALAVADE , Aliasgar S. MADRASWALA , Yogesh B. WAKCHAURE
摘要： Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.
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