公开(公告)号：US20190006016A1

公开(公告)日：2019-01-03

申请号：US15638260

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Shantanu R. RAJWADE ,  Aliasgar S. MADRASWALA ,  Uday CHANDRASEKHAR ,  Purval S. SULE ,  Sagar UPADHYAY

IPC: G11C16/34 ,  G11C16/10 ,  G11C8/06 ,  G11C8/10 ,  G06F11/14

Abstract: A programming of a memory device configurable to reach a plurality of voltage levels is initiated. For each voltage level to be reached, a checkpoint is set up within a sequence of program pulses applied for the programming of the memory device, to determine whether a plurality of memory cells of the memory device have reached the voltage level. The programming of the memory device is aborted, in response to determining at the checkpoint that the plurality of memory cells have not reached the voltage level.

公开(公告)号：US20190252033A1

公开(公告)日：2019-08-15

申请号：US16168809

申请日：2018-10-23

Applicant: Intel Corporation

Inventor： Varsha REGULAPATI ,  Heonwook KIM ,  Aliasgar S. MADRASWALA ,  Naga Kiranmayee UPADHYAYULA ,  Purval S. SULE ,  Jong Tai PARK ,  Sriram BALASUBRAHMANYAM ,  Manjiri M. KATMORE

IPC: G11C29/02 ,  G11C16/32 ,  G11C16/04 ,  G06F13/16 ,  G06F12/02

CPC classification number: G11C29/023 ,  G06F12/0246 ,  G06F13/1668 ,  G11C16/0483 ,  G11C16/32 ,  G11C29/028

Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.