公开(公告)号：US10691182B2

公开(公告)日：2020-06-23

申请号：US16416753

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Simon C. Steely, Jr. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

IPC: H05K1/18 ,  G06F1/18 ,  H01L23/538 ,  G06F15/76 ,  H01L25/065 ,  G06F9/50

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

公开(公告)号：US10417175B2

公开(公告)日：2019-09-17

申请号：US15859466

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming ,  Simon C. Steely, Jr. ,  Kent D. Glossop

IPC: G06F15/16 ,  G06F15/173 ,  G06F9/54

Abstract: Methods and apparatuses relating to consistency in an accelerator are described. In one embodiment, request address file (RAF) circuits are coupled to a spatial array by a first network, a memory is coupled to the RAF circuits by a second network, a RAF circuit is to not issue, into the second network, a request to the memory marked with a program order dependency on a previous request until receiving a first token generated by completion of the previous request to the memory by another RAF circuit, and a second RAF circuit is to not issue, into the second network, a second request to the memory marked with a program order dependency on a first request until receiving a second token sent by a first RAF circuit when a predetermined time period has lapsed since the first request was issued by the first RAF circuit into the second network.

公开(公告)号：US10387319B2

公开(公告)日：2019-08-20

申请号：US15640534

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Michael C. Adler ,  Chiachen Chou ,  Neal C. Crago ,  Kermin Fleming ,  Kent D. Glossop ,  Aamer Jaleel ,  Pratik M. Marolia ,  Simon C. Steely, Jr. ,  Samantika S. Sury

IPC: G06F12/0802 ,  G06F15/00 ,  G06F12/0862 ,  H03K19/177 ,  G06F15/78 ,  G11C8/12 ,  G06F17/50 ,  G06F15/80

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.

公开(公告)号：US10379855B2

公开(公告)日：2019-08-13

申请号：US15283259

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： William C. Hasenplaugh ,  Chris J. Newburn ,  Simon C. Steely, Jr. ,  Samantika S. Sury

IPC: G06F9/312 ,  G06F12/00 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/0886 ,  G06F12/0897 ,  G06F12/126 ,  G06F12/1027

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.

公开(公告)号：US10275243B2

公开(公告)日：2019-04-30

申请号：US15201442

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Edward T. Grochowski ,  Asit K. Mishra ,  Robert Valentine ,  Mark J. Charney ,  Simon C. Steely, Jr.

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

公开(公告)号：US12204898B2

公开(公告)日：2025-01-21

申请号：US18240287

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Edward T. Grochowski ,  Asit K. Mishra ,  Robert Valentine ,  Mark J. Charney ,  Simon C. Steely, Jr.

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

公开(公告)号：US12204478B2

公开(公告)日：2025-01-21

申请号：US17206961

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Swapna Raj ,  Samantika S. Sury ,  Kermin Chofleming ,  Simon C. Steely, Jr.

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16

Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.

公开(公告)号：US11086816B2

公开(公告)日：2021-08-10

申请号：US15719281

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Kermin Fleming ,  Simon C. Steely, Jr. ,  Kent D. Glossop

IPC: G06F15/80

Abstract: Systems, methods, and apparatuses relating to debugging a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. At least a first of the plurality of processing elements is to enter a halted state in response to being represented as a first of the plurality of dataflow operators.

公开(公告)号：US11068264B2

公开(公告)日：2021-07-20

申请号：US16537318

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： William C. Hasenplaugh ,  Chris J. Newburn ,  Simon C. Steely, Jr. ,  Samantika S. Sury

IPC: G06F9/312 ,  G06F9/34 ,  G06F12/08 ,  G06F9/30 ,  G06F12/0886 ,  G06F12/0897 ,  G06F12/126 ,  G06F12/1045 ,  G06F12/1027 ,  G06F9/38

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.

公开(公告)号：US10515046B2

公开(公告)日：2019-12-24

申请号：US15640543

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Kermin Fleming ,  Kent D. Glossop ,  Simon C. Steely, Jr.

IPC: G06F13/42 ,  G06F9/50 ,  G06F15/82

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a synchronizer circuit coupled between an interconnect network of a first tile and an interconnect network of a second tile and comprising storage to store data to be sent between the interconnect network of the first tile and the interconnect network of the second tile, the synchronizer circuit to convert the data from the storage between a first voltage or a first frequency of the first tile and a second voltage or a second frequency of the second tile to generate converted data, and send the converted data between the interconnect network of the first tile and the interconnect network of the second tile