公开(公告)号：US09473259B2

公开(公告)日：2016-10-18

申请号：US14550822

申请日：2014-11-21

Applicant: INTEL CORPORATION

Inventor： Itamar Levin ,  Kevan A. Lillie ,  Dima Hammed ,  Elior Segev ,  Mingming Xu ,  Tomer Fael

IPC: H04B17/00 ,  H04B17/24 ,  H04B17/29 ,  H04L25/03

CPC classification number: H04B17/24 ,  G06F11/221 ,  H04B17/00 ,  H04B17/29 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03878

Abstract: Various embodiments are generally directed to techniques for testing a receiver incorporated into an IC to receive a bitstream. An apparatus includes a precharge component to set a VGA to output a differential bias voltage; a taps component to set a tap to form a feedback loop that extends from an output of the bit slicer to the input of the bit slicer through a delay circuit and the tap, the tap to output a first differential voltage to the input of the bit slicer to invert a polarity of a sum of differential voltages at the input of the bit slicer to enable oscillation of the bit slicer, the sum generated from at least the differential bias voltage and the first differential voltage; and a capture component coupled to the output of the bit slicer to capture a series of bit values therefrom. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及用于测试结合到IC中以接收比特流的接收机的技术。 一种装置包括：预充电部件，用于设置VGA以输出差分偏置电压; 抽头分量，用于设置抽头以形成反馈环路，该反馈环路通过延迟电路和抽头从位限幅器的输出延伸到位限幅器的输入，该抽头将第一差分电压输出到位的输入端 切片器，以在位限幅器的输入处反转差分电压之和的极性，以使得位限幅器的振荡，至少从差分偏置电压和第一差分电压产生的和; 以及耦合到所述位限幅器的输出以从其捕获一系列位值的捕获元件。 描述和要求保护其他实施例。

公开(公告)号：US09973356B1

公开(公告)日：2018-05-15

申请号：US15475690

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ram Livne ,  Ro'ee Eitan ,  Yoel Krupnik ,  Vladislav Tsirkin ,  Tomer Fael ,  Dror Lazar ,  Ariel Cohen ,  Alexander Pogrebinsky ,  Adee Ofir Ran

IPC: H03L7/08 ,  H04L25/03 ,  H03G3/20 ,  H04L25/06

CPC classification number: H04L25/03057

Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.