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    Variable composition transparent conductive oxide layer and methods of forming thereof
    2.
    发明授权
    Variable composition transparent conductive oxide layer and methods of forming thereof 有权
    可变组合物透明导电氧化物层及其形成方法

    公开(公告)号：US09391232B1

    公开(公告)日：2016-07-12

    申请号：US14577967

    申请日：2014-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Minh Huu Le ,  Jianhua Hu

    IPC: H01L33/42 ,  H01L33/00 ,  H01L33/38

    CPC classification number: H01L33/005 ,  H01L33/38 ,  H01L33/42 ,  H01L2933/0016 ,  H01L2933/0033 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2933/0091

    Abstract: Provided are light emitting diodes (LEDs) and methods of fabricating such LEDs. An LED may include a transparent conductive oxide (TCO) layer having a varying refractive index. For example, the refractive index may be higher at the interface of the TCO layer with an epitaxial stack than on the side of the TCO layer. The refractive index variability allows reducing light intensity losses in the LED. The refractive index variability may be achieved by feeding a substrate through a deposition chamber having a variable concentration of at least one process gas, such as oxygen. Specifically, the concentration of the process gas may be higher at one slit opening than at another slit opening. As the substrate moves through the deposition chamber, the TCO layer is continuously deposited. Due to the concentration variability, the resulting TCO layer may have a variable composition throughout the thickness of the TCO layer.

    Abstract translation: 提供了发光二极管（LED）和制造这种LED的方法。 LED可以包括具有变化的折射率的透明导电氧化物（TCO）层。 例如，在具有外延堆叠的TCO层的界面处的折射率可以高于在TCO层的侧面上的折射率。 折射率变化允许减少LED中的光强度损失。 折射率可变性可以通过将衬底通过具有可变浓度的至少一种工艺气体（例如氧气）的沉积室进行。 具体地，处理气体的浓度在一个狭缝开口处可以比在另一个狭缝开口处更高。 当衬底移动通过沉积室时，TCO层被连续沉积。 由于浓度变化，所得的TCO层可以在TCO层的整个厚度上具有可变的组成。

    Low-E Panels and Methods of Forming the Same
    3.
    发明申请
    Low-E Panels and Methods of Forming the Same 审中-公开
    低E面板及其形成方法

    公开(公告)号：US20160122235A1

    公开(公告)日：2016-05-05

    申请号：US14531643

    申请日：2014-11-03

    Applicant: Intermolecular Inc.

    Inventor： Guizhen Zhang ,  Guowen Ding ,  Tong Ju ,  Minh Huu Le ,  Daniel Schweigert

    IPC: C03C17/36

    CPC classification number: C03C17/366 ,  C03C17/36 ,  C03C17/3602 ,  C03C17/3618 ,  C03C17/3626 ,  C03C17/3639 ,  C03C17/3642 ,  C03C17/3644 ,  C03C17/3681 ,  C03C2218/155

    Abstract: Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A first dielectric layer is formed above the transparent substrate. The first dielectric layer includes zinc, tin, and aluminum. A first reflective layer is formed above the first dielectric layer. A second dielectric layer is formed above the first reflective layer. The second dielectric layer includes zinc, tin, and aluminum. A second reflective layer is formed above the second dielectric layer.

    Abstract translation: 本文提供的实施例描述了用于形成低e板的低e板和方法。 提供透明基板。 在透明基板的上方形成第一电介质层。 第一介电层包括锌，锡和铝。 第一反射层形成在第一介电层的上方。 在第一反射层上方形成第二电介质层。 第二电介质层包括锌，锡和铝。 第二反射层形成在第二介电层的上方。

    Zinc Stannate Ohmic Contacts for P-Type Gallium Nitride
    5.
    发明申请
    Zinc Stannate Ohmic Contacts for P-Type Gallium Nitride 有权
    锡锡酸盐欧姆接触P型氮化镓

    公开(公告)号：US20150311397A1

    公开(公告)日：2015-10-29

    申请号：US14259387

    申请日：2014-04-23

    Applicant: INTERMOLECULAR, INC.

    Inventor： Jianhua Hu ,  Heng Kai Hsu ,  Tong Ju ,  Minh Huu Le ,  Sandeep Nijhawan ,  Teresa B. Sapirman

    IPC: H01L33/42 ,  H01L33/32

    CPC classification number: H01L33/42 ,  H01L33/32 ,  H01L33/40 ,  H01L33/483 ,  H01L2933/0016

    Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (≧4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.

    Abstract translation: 由锡酸锡（例如ZnSnO 3）制造对p-GaN和其它高功函数（≥4.2eV）的半导体的透明欧姆接触。 ZnO和SnO2可以从单独的靶溅射并退火以形成锡酸锌。 可以在1:2和2:1之间的范围内调整Zn：Sn比，以优化特定半导体和感兴趣的波长的带隙，功函数，电导率和透明度。 可以通过使锡酸锌结晶，通过掺入高达5重量％的Al或In或两者来改善电导率。

    CAAC IGZO Deposited at Room Temperature
    6.
    发明申请
    CAAC IGZO Deposited at Room Temperature 审中-公开
    CAAC IGZO在室温下沉积

    公开(公告)号：US20150279674A1

    公开(公告)日：2015-10-01

    申请号：US14511475

    申请日：2014-10-10

    Applicant: Intermolecular, Inc.

    Inventor： Seon-Mee Cho ,  Sang Lee ,  Minh Huu Le

    IPC: H01L21/02 ,  H01L29/786 ,  H01L29/04 ,  C23C14/14

    CPC classification number: H01L21/02631 ,  C23C14/0036 ,  C23C14/086 ,  C23C14/352 ,  C23C14/562 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/045 ,  H01L29/66969 ,  H01L29/7869

    Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The third target includes a compound of indium oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, when deposited at room temperature, without the need of a subsequent anneal treatment.

    Abstract translation: 使用共溅射技术使用PVD沉积In-Ga-Zn-O膜。 膜在包括氧和氩的气氛中沉积。 约300℃的加热器设定值导致衬底温度为约165℃。一个靶包括In，Ga，Zn和O的合金，原子比为In：Ga：Zn为约1:1:1的原子比。 第二靶标包括氧化锌的化合物。 第三靶包括氧化铟的化合物。 当在室温下沉积时，膜以沉积状态呈现c轴对准的结晶（CAAC）相，而不需要随后的退火处理。

    Silver based conductive layer for flexible electronics
    7.
    发明授权
    Silver based conductive layer for flexible electronics 有权
    用于柔性电子元件的银基导电层

    公开(公告)号：US09121100B2

    公开(公告)日：2015-09-01

    申请号：US13715477

    申请日：2012-12-14

    Applicant: Intermolecular Inc.

    Inventor： Mohd Fadzli Anwar Hassan ,  Guowen Ding ,  Minh Huu Le ,  Minh Anh Anh Nguyen ,  Zhi-Wen Wen Sun ,  Guizhen Zhang

    IPC: C23C28/00 ,  C23C30/00 ,  H01L51/52 ,  H01L51/00

    CPC classification number: H05K1/092 ,  C23C28/42 ,  C23C30/00 ,  H01L51/0097 ,  H01L51/5234 ,  H05K1/0274 ,  Y10T428/265

    Abstract: Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1.5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack to have an improved ductility property.

    Abstract translation: 制造导电叠层的方法包括形成夹在两层透明导电氧化物（例如氧化铟锡（ITO））之间的掺杂或合金化的银层。 掺杂的银或银合金层可以是薄的，例如在1.5至20nm之间，因此可以是透明的。 掺杂的银或银合金可以提供改善的延展性，允许导电叠层可弯曲。 透明导电氧化物层也可以是薄的，允许导电叠层具有改善的延展性。

    High Productivity Combinatorial material screening for stable, high-mobility non-silicon thin film transistors
    9.
    发明授权
    High Productivity Combinatorial material screening for stable, high-mobility non-silicon thin film transistors 有权
    高生产率组合材料筛选稳定的高迁移率非硅薄膜晶体管

    公开(公告)号：US09105527B2

    公开(公告)日：2015-08-11

    申请号：US14135086

    申请日：2013-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Jeroen Van Duren ,  Sang Lee ,  Minh Huu Le

    IPC: H01L21/16 ,  H01L27/12 ,  H01L21/02 ,  H01L21/465 ,  H01L21/66

    CPC classification number: H01L27/1259 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/465 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

    Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

    Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅极介电沉积，栅极电介质图案化，基于金属的半导体沉积，基于金属的图案化，蚀刻停止沉积，蚀刻停止图案化，源极/漏极沉积或源极/漏极图案化中的至少一个。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

    High productivity combinatorial material screening for metal oxide films
    10.
    发明授权
    High productivity combinatorial material screening for metal oxide films 有权
    用于金属氧化物膜的高生产率组合材料筛选

    公开(公告)号：US09105526B2

    公开(公告)日：2015-08-11

    申请号：US14134571

    申请日：2013-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Minh Huu Le ,  Sang Lee ,  Jeroen Van Duren

    IPC: H01L21/16 ,  H01L27/12 ,  H01L21/02 ,  H01L21/66

    CPC classification number: H01L21/02565 ,  H01L21/02554 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78693

    Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) deposition, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

    Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅极介电沉积，栅极电介质图案化，金属基半导体（例如ZnO x，ZnSnO x，ZnInO x或ZnGaO x）沉积，金属基半导体（例如ZnO x，ZnSnO x，ZnInO x或ZnGaO x）中的至少一种， 图案化，蚀刻停止沉积，蚀刻停止图案化，源极/漏极沉积或源极/漏极图案化。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

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