公开(公告)号：US20150380530A1

公开(公告)日：2015-12-31

申请号：US14848355

申请日：2015-09-09

Applicant: Industrial Technology Research Institute

Inventor： Jing-Yi Yan ,  Chih-Chieh Hsu ,  Hsiao-Chiang Yao ,  Chu-Yin Hung

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/66765 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Abstract translation: 半导体器件包括栅极，第一电极，第一绝缘层，有源层，蚀刻停止层，第二绝缘层，源极，漏极和第二电极。 第一绝缘层覆盖栅极和第一电极。 有源层和蚀刻停止层分别设置在栅极和第一电极上的第一绝缘层上。 第二绝缘层覆盖有源层和蚀刻停止层，并且具有暴露有源层的第一开口和第二开口以及露出蚀刻停止层的第三开口。 源极和漏极设置在第二绝缘层上，并且分别通过第一开口和第二开口与有源层接触。 第二电极位于第二绝缘层上，并通过第三开口与蚀刻停止层接触。

公开(公告)号：US10083989B2

公开(公告)日：2018-09-25

申请号：US15209780

申请日：2016-07-14

Applicant: Industrial Technology Research Institute

Inventor： Tai-Jui Wang ,  Tsu-Chiang Chang ,  Yu-Hua Chung ,  Wei-Han Chen ,  Hsiao-Chiang Yao

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1218 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.

公开(公告)号：US20190140106A1

公开(公告)日：2019-05-09

申请号：US15913897

申请日：2018-03-06

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Tai-Jui Wang ,  Yung-Hui Yeh ,  Jui-Wen Yang ,  Hsiao-Chiang Yao ,  Chun-Hung Chu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L27/12 ,  H01L21/02 ,  C23C16/24 ,  C23C16/34 ,  C23C16/40 ,  H01L51/05

Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.

公开(公告)号：US09786790B2

公开(公告)日：2017-10-10

申请号：US15062222

申请日：2016-03-07

Applicant: Industrial Technology Research Institute

Inventor： Ching-Wen Su ,  Tai-Jui Wang ,  Hsiao-Chiang Yao ,  Tsu-Chiang Chang ,  Bo-Yuan Su

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/324 ,  H01L23/552

CPC classification number: H01L29/78675 ,  H01L21/324 ,  H01L23/552 ,  H01L27/1218 ,  H01L29/78603 ,  H01L29/78633

Abstract: In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer.

公开(公告)号：US20170170329A1

公开(公告)日：2017-06-15

申请号：US15062222

申请日：2016-03-07

Applicant: Industrial Technology Research Institute

Inventor： Ching-Wen Su ,  Tai-Jui Wang ,  Hsiao-Chiang Yao ,  Tsu-Chiang Chang ,  Bo-Yuan Su

IPC: H01L29/786 ,  H01L21/324 ,  H01L23/552

CPC classification number: H01L29/78675 ,  H01L21/324 ,  H01L23/552 ,  H01L27/1218 ,  H01L29/78603 ,  H01L29/78633

Abstract: In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer.

公开(公告)号：US20170170207A1

公开(公告)日：2017-06-15

申请号：US15209780

申请日：2016-07-14

Applicant: Industrial Technology Research Institute

Inventor： Tai-Jui Wang ,  Tsu-Chiang Chang ,  Yu-Hua Chung ,  Wei-Han Chen ,  Hsiao-Chiang Yao

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1218 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.

公开(公告)号：US09553176B2

公开(公告)日：2017-01-24

申请号：US14848355

申请日：2015-09-09

Applicant: Industrial Technology Research Institute

Inventor： Jing-Yi Yan ,  Chih-Chieh Hsu ,  Hsiao-Chiang Yao ,  Chu-Yin Hung

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/66765 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Abstract translation: 半导体器件包括栅极，第一电极，第一绝缘层，有源层，蚀刻停止层，第二绝缘层，源极，漏极和第二电极。 第一绝缘层覆盖栅极和第一电极。 有源层和蚀刻停止层分别设置在栅极和第一电极上的第一绝缘层上。 第二绝缘层覆盖有源层和蚀刻停止层，并且具有暴露有源层的第一开口和第二开口以及露出蚀刻停止层的第三开口。 源极和漏极设置在第二绝缘层上，并且分别通过第一开口和第二开口与有源层接触。 第二电极位于第二绝缘层上，并通过第三开口与蚀刻停止层接触。