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    Semiconductor arrangements
    1.
    发明授权
    Semiconductor arrangements 有权

    公开(公告)号：US11315906B2

    公开(公告)日：2022-04-26

    申请号：US16775632

    申请日：2020-01-29

    Applicant: Infineon Technologies AG

    Inventor： Daniel Domes

    IPC: H01L25/07 ,  H01L23/367 ,  H01L23/50 ,  H01L25/18

    Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between a first terminal and a second terminal, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. The switching devices of the first type and the switching devices of the second type are arranged in a power semiconductor module that has first and second longitudinal sides and first and second narrow sides. The switching devices of the first type and the switching devices of the second type are arranged next to each other in at least one row extending in a first horizontal direction that is parallel to the first and second longitudinal sides, such that within each of the at least one rows no more than two switching devices of the same type are arranged in direct succession.

    Semiconductor Module Arrangement
    2.
    发明申请
    Semiconductor Module Arrangement 有权

    公开(公告)号：US20210028078A1

    公开(公告)日：2021-01-28

    申请号：US16937701

    申请日：2020-07-24

    Applicant: Infineon Technologies AG

    Inventor： Daniel Domes

    IPC: H01L23/049 ,  H01L23/373 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18

    Abstract: A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

    Semiconductor Arrangements
    3.
    发明申请
    Semiconductor Arrangements 审中-公开

    公开(公告)号：US20200243489A1

    公开(公告)日：2020-07-30

    申请号：US16775632

    申请日：2020-01-29

    Applicant: Infineon Technologies AG

    Inventor： Daniel Domes

    IPC: H01L25/07 ,  H01L25/18 ,  H01L23/50 ,  H01L23/367

    Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between a first terminal and a second terminal, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. The switching devices of the first type and the switching devices of the second type are arranged in a power semiconductor module that has first and second longitudinal sides and first and second narrow sides. The switching devices of the first type and the switching devices of the second type are arranged next to each other in at least one row extending in a first horizontal direction that is parallel to the first and second longitudinal sides, such that within each of the at least one rows no more than two switching devices of the same type are arranged in direct succession.

    Semiconductor arrangements
    5.
    发明授权
    Semiconductor arrangements 有权

    公开(公告)号：US11973065B2

    公开(公告)日：2024-04-30

    申请号：US17676410

    申请日：2022-02-21

    Applicant: Infineon Technologies AG

    Inventor： Daniel Domes

    IPC: H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H02M7/00

    CPC classification number: H01L25/072 ,  H01L23/367 ,  H01L23/50 ,  H01L25/18

    Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.

    Semiconductor module arrangement
    7.
    发明授权
    Semiconductor module arrangement 有权

    公开(公告)号：US11538725B2

    公开(公告)日：2022-12-27

    申请号：US16937701

    申请日：2020-07-24

    Applicant: Infineon Technologies AG

    Inventor： Daniel Domes

    IPC: H01L23/049 ,  H01L23/373 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18

    Abstract: A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

    Drive circuit for reverse-conducting IGBTs
    8.
    发明授权
    Drive circuit for reverse-conducting IGBTs 有权

    公开(公告)号：US09698772B2

    公开(公告)日：2017-07-04

    申请号：US14862582

    申请日：2015-09-23

    Applicant: Infineon Technologies AG

    Inventor： Daniel Domes

    IPC: H03K17/567

    CPC classification number: H03K17/567 ,  H03K2217/0036

    Abstract: A drive circuit includes a first output node for connection to the control electrode of the semiconductor switch, a voltage supply circuit, and a first switching stage connected to the voltage supply and a second switching stage connected to the voltage supply. A first resistor network is connected between the first switching stage and the first output node. A second resistor network is connected between the second switching stage and the first output node. A control logic is designed to generate control signals for the guiding of the first switching stage and the second switching stage in such a way that in a first operating mode of the semiconductor switch the semiconductor switch is driven only via the first resistor network, and in a second operating mode of the semiconductor switch the semiconductor switch is driven only via the second resistor network or both resistor networks.

    Semiconductor module arrangement
    10.
    发明授权
    Semiconductor module arrangement 有权

    公开(公告)号：US11942452B2

    公开(公告)日：2024-03-26

    申请号：US16939130

    申请日：2020-07-27

    Applicant: Infineon Technologies AG

    Inventor： Christian Robert Mueller ,  Andressa Colvero Schittler ,  Daniel Domes ,  Andre Lenze

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/049 ,  H01L23/367 ,  H01L23/538 ,  H01L23/64

    CPC classification number: H01L25/0655 ,  H01L23/049 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/48225

    Abstract: A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

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