公开(公告)号：US20250107128A1

公开(公告)日：2025-03-27

申请号：US18895557

申请日：2024-09-25

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Hans-Joachim Schulze ,  Vera van Treek

IPC: H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/66 ,  H01L29/866

Abstract: A power semiconductor device includes: a semiconductor body that conducts a load current between first and second load terminals at opposite first and second sides; a drift region of a first conductivity type; trenches extending from the first side towards the second side and each including a trench electrode; mesas laterally confined by the trenches and each including first and second type mesas; and semiconductor structures each including a serial connection of a first region of the first conductivity type coupled to or formed by the drift region, a second region of a second conductivity type and a third region of the first conductivity type coupled to the first load terminal by at least one of a first ohmic resistor and a Zener diode. Each first type mesa is electrically connected to the first load terminal and devoid of the semiconductor structures which are arranged in the second type mesas.

公开(公告)号：US20240304709A1

公开(公告)日：2024-09-12

申请号：US18583993

申请日：2024-02-22

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Roman Baburske ,  Frank Pfirsch ,  Franz Josef Niedernostheide

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/06 ,  H01L29/43 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L27/0207 ,  H01L29/0603 ,  H01L29/435 ,  H01L29/66333

Abstract: A semiconductor device includes a semiconductor body having a trench transistor cell array. The trench transistor cell array includes a first trench transistor cell unit and a second trench transistor cell unit. Transistor cells based on the first trench transistor cell unit and transistor cells based on the second trench transistor cell unit are electrically connected in parallel. The first trench transistor cell unit has a first threshold voltage. The second trench transistor cell unit has a second threshold voltage larger than the first threshold voltage. An absolute value of dU/dt at turning on a nominal current of the transistor cell array is at least 50% of an absolute value of dU/dt at turning on 10% of the nominal current of the transistor cell array, dU/dt being the temporal derivate of a voltage U between load terminals of the trench transistor cell array.

公开(公告)号：US20230307531A1

公开(公告)日：2023-09-28

申请号：US18122918

申请日：2023-03-17

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Frank Pfirsch ,  Jana Hänsel ,  Katja Waschneck

IPC: H01L29/739 ,  H01L29/10 ,  H03K17/567

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H03K17/567

Abstract: A power semiconductor device includes: a semiconductor body coupled to first and second load terminals; an active region with first and second sections, both configured to conduct a load current between the load terminals; electrically isolated from the load terminals, first control electrodes in the first section and second control electrodes in both the first and second sections); and semiconductor channel structures in the semiconductor body extending in both the first and second sections. Each channel structure is associated to at least one of the first and second control electrodes. The respective control electrode is configured to induce an inversion channel for load current conduction in the associated semiconductor channel structure. The first section exhibits a first effective total inversion channel width per unit area ratio, W/A1, and the second section exhibits a second effective inversion channel width per unit area ratio, W/A2, where W/A1>W/A2.

公开(公告)号：US10608104B2

公开(公告)日：2020-03-31

申请号：US14228881

申请日：2014-03-28

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Johannes Georg Laven ,  Christian Jaeger ,  Frank Wolter ,  Frank Pfirsch ,  Antonio Vellei

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739

Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.

公开(公告)号：US20160005818A1

公开(公告)日：2016-01-07

申请号：US14854396

申请日：2015-09-15

Applicant: Infineon Technologies AG

Inventor： Christian Philipp Sandow ,  Hans-Joachim Schulze ,  Johannes Georg Laven ,  Franz-Josef Niedernostheide ,  Frank Pfirsch ,  Hans-Peter Felsl

IPC: H01L29/10 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397

Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.

Abstract translation: IGBT包括至少一个第一类型晶体管单元，包括基极区，第一和第二发射极区以及布置在第一发射极区和基极区之间的体区。 基部区域布置在体区和第二发射区之间。 邻近体区的栅电极通过栅极电介质与体区绝缘绝缘。 与基极相邻的基极通过基极电介质与基极区域介电绝缘。 基极区域具有邻接基极电介质的第一基极区域和布置在第二发射极区域与第一基极区域之间的第二基极区域区域。 第一基极区域的掺杂浓度与第二基极区域的掺杂浓度之比至少为10.基极电介质比栅极电介质厚。

公开(公告)号：US20150333161A1

公开(公告)日：2015-11-19

申请号：US14278519

申请日：2014-05-15

Applicant: Infineon Technologies AG

Inventor： Vera Van Treek ,  Frank Pfirsch ,  Roman Baburske ,  Franz-Josef Niedernostheide

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7397

Abstract: A semiconductor component is described herein. In accordance with one example of the invention, the semiconductor component includes a semiconductor body, which has a top surface and a bottom surface. A body region, which is doped with dopants of a second doping type, is arranged at the top surface of the semiconductor body. A drift region is arranged under the body region and doped with dopants of a first doping type, which is complementary to the second doping type. Thus a first pn-junction is formed at the transition between the body region and the drift region. A field stop region is arranged under the drift region and adjoins the drift region. The field stop region is doped with dopants of the same doping type as the drift region. However, the concentration of dopants in the field stop region is higher than the concentration of dopants in the drift region. At least one pair of semiconductor layers composed of a first and a second semiconductor layer are arranged in the drift region. The first semiconductor layer extends substantially parallel to the top surface of the semiconductor body and is doped with dopants of the first doping type but with a higher concentration of dopants than the drift region. The second semiconductor layer is arranged adjacent to or adjoining the first semiconductor layer and is doped with dopants of the second doping type. Furthermore, the second semiconductor layer is structured to include openings so that a vertical current path is provided through the drift region without an intervening pn-junction.

Abstract translation: 本文描述了半导体部件。 根据本发明的一个示例，半导体部件包括具有顶表面和底表面的半导体本体。 掺杂有第二掺杂类型的掺杂剂的体区设置在半导体本体的顶表面。 漂移区布置在体区下方并掺杂有与第二掺杂类型互补的第一掺杂类型的掺杂剂。 因此，在身体区域和漂移区域之间的过渡处形成第一pn结。 漂移区域下方设置场停止区域，并与漂移区域相邻。 场停止区域掺杂有与漂移区相同的掺杂类型的掺杂剂。 然而，场停止区域中的掺杂剂的浓度高于漂移区域中的掺杂剂的浓度。 在漂移区域中布置由第一和第二半导体层组成的至少一对半导体层。 第一半导体层基本上平行于半导体本体的顶表面延伸，并掺杂有第一掺杂类型的掺杂剂，但具有比漂移区更高的掺杂剂浓度。 第二半导体层被布置为与第一半导体层相邻或相邻，并且掺杂有第二掺杂类型的掺杂剂。 此外，第二半导体层被构造成包括开口，使得通过漂移区域提供垂直电流路径，而没有中间pn结。

公开(公告)号：US09166027B2

公开(公告)日：2015-10-20

申请号：US14041094

申请日：2013-09-30

Applicant: Infineon Technologies AG

Inventor： Christian Philipp Sandow ,  Hans-Joachim Schulze ,  Johannes Georg Laven ,  Franz-Josef Niedernostheide ,  Frank Pfirsch ,  Hans-Peter Felsl

IPC: H01L29/739

CPC classification number: H01L29/1095 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397

Abstract: An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body region is arranged between the first emitter region and the base region. The base region is arranged between the body region and the second emitter region. The IGBT further includes a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a base electrode adjacent the base region and dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A doping concentration of the first base region section is higher than a doping concentration of the second base region section.

Abstract translation: IGBT包括至少一个第一类型晶体管单元，其包括基极区，第一发射区，体区和第二发射极区。 体区布置在第一发射区和基区之间。 基部区域布置在主体区域和第二发射区域之间。 IGBT还包括与主体区域相邻并且通过栅极电介质与体区电介绝缘的栅极电极和与基极区域相邻并且与基极区域由基极电介质电介质绝缘的基极。 基极区域具有邻接基极电介质的第一基极区域和布置在第二发射极区域与第一基极区域之间的第二基极区域区域。 第一基极区域的掺杂浓度高于第二基极区域的掺杂浓度。

公开(公告)号：US20150236143A1

公开(公告)日：2015-08-20

申请号：US14185117

申请日：2014-02-20

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber

IPC: H01L29/739 ,  H01L21/266 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/407 ,  H01L29/66348

Abstract: A semiconductor device includes a drift zone of a first conductivity type in a semiconductor body. Controllable cells are configured to form a conductive channel connected with the drift zone in a first state. First zones of the first conductivity type as well as second zones and a third zone of a complementary second conductivity type are between the drift zone and a rear side electrode, respectively. The first, second and third zones directly adjoin the rear side electrode. The third zone is larger and has a lower mean emitter efficiency than the second zones.

Abstract translation: 半导体器件包括半导体本体中的第一导电类型的漂移区。 可控电池被配置为在第一状态下形成与漂移区连接的导电通道。 第一导电类型的第一区以及第二区和互补第二导电类型的第三区分别位于漂移区和后侧电极之间。 第一，第二和第三区域直接毗邻后侧电极。 第三个区域比第二个区域更大，平均发射器效率更低。

公开(公告)号：US20150179637A1

公开(公告)日：2015-06-25

申请号：US14561357

申请日：2014-12-05

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Carsten Schaeffer

IPC: H01L27/06 ,  H01L29/47 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0635 ,  H01L27/0727 ,  H01L29/0615 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.

Abstract translation: 半导体器件包括从半导体衬底的主表面延伸到半导体衬底中的第一掺杂区域。 此外，半导体器件包括邻近第一掺杂区布置的第二掺杂区。 第一掺杂区域包括从半导体衬底的主表面延伸到第二掺杂区域的至少一个低掺杂剂量部分。 第一掺杂区域的低掺杂剂量部分内的掺杂剂量小于击穿电荷的3倍。 另外，半导体器件包括与半导体衬底的主表面处的第一掺杂区域接触的第一电极结构。 第一电极结构在半导体衬底的主表面上的功函数大于4.9eV或低于4.4eV。

公开(公告)号：US20150109050A1

公开(公告)日：2015-04-23

申请号：US14551632

申请日：2014-11-24

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H03K17/66 ,  H03K3/01 ,  H01L29/739

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据一种方法的实施例，半导体器件在反向偏置单极模式下工作，然后在正向偏置模式中将半导体器件操作为截止状态。 半导体器件包括设置在器件的单元区域外的至少一个浮置寄生区域。