公开(公告)号：US20220059659A1

公开(公告)日：2022-02-24

申请号：US17519161

申请日：2021-11-04

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US11195921B2

公开(公告)日：2021-12-07

申请号：US16412131

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/76 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US20210118986A1

公开(公告)日：2021-04-22

申请号：US17111551

申请日：2020-12-04

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US11888032B2

公开(公告)日：2024-01-30

申请号：US18073860

申请日：2022-12-02

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7813

Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

公开(公告)号：US11462611B2

公开(公告)日：2022-10-04

申请号：US17111551

申请日：2020-12-04

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US20210050421A1

公开(公告)日：2021-02-18

申请号：US16986338

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

公开(公告)号：US20190355819A1

公开(公告)日：2019-11-21

申请号：US16412131

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US12266694B2

公开(公告)日：2025-04-01

申请号：US18398823

申请日：2023-12-28

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

公开(公告)号：US20240136406A1

公开(公告)日：2024-04-25

申请号：US18398823

申请日：2023-12-28

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7813

Abstract: A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

公开(公告)号：US11881512B2

公开(公告)日：2024-01-23

申请号：US17519161

申请日：2021-11-04

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7828

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.