公开(公告)号：US11133256B2

公开(公告)日：2021-09-28

申请号：US16446920

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

公开(公告)号：US11749606B2

公开(公告)日：2023-09-05

申请号：US17371293

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/5383 ,  H01L28/20 ,  H01L28/40 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

公开(公告)号：US11437294B2

公开(公告)日：2022-09-06

申请号：US16059513

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit Kumar Jain ,  Kaladhar Radhakrishnan ,  Jonathan P. Douglas ,  Chin Lee Kuan

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  G06F1/20

Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

公开(公告)号：US11380623B2

公开(公告)日：2022-07-05

申请号：US15939162

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Chin Lee Kuan ,  Amit Kumar Jain

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01F27/36 ,  H05K9/00

Abstract: Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.

公开(公告)号：US20190304915A1

公开(公告)日：2019-10-03

申请号：US16446920

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

IPC: H01L23/538 ,  H01L49/02

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

公开(公告)号：US11502603B2

公开(公告)日：2022-11-15

申请号：US16452322

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Chin Lee Kuan ,  Sameer Shekhar

IPC: H02M3/158 ,  H01F27/28 ,  G01R19/165 ,  G06F1/26 ,  H01F27/40 ,  G01R33/028 ,  H02M3/156 ,  H02M1/00

Abstract: Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.

公开(公告)号：US20200098674A1

公开(公告)日：2020-03-26

申请号：US16142249

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Amit Kumar Jain ,  Sameer Shekhar

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments may relate to a semiconductor package. A conductive frame may be coupled with the semiconductor package. The conductive frame may include a first portion, a second portion, and a third portion positioned between the first portion and the second portion. The first portion may be coupled with the first side of the semiconductor package. The second portion may be coupled with the second side of the semiconductor package. The third portion may be coupled with the sidewall of the semiconductor package. Other embodiments may be described or claimed.

公开(公告)号：US11175709B2

公开(公告)日：2021-11-16

申请号：US16551523

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Mark Carbone ,  Merwin M. Brown

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3206

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.

公开(公告)号：US20210335712A1

公开(公告)日：2021-10-28

申请号：US17371293

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

公开(公告)号：US20190384367A1

公开(公告)日：2019-12-19

申请号：US16551523

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Mark Carbone ,  Merwin M. Brown

IPC: G06F1/20 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.