公开(公告)号：US20220137860A1

公开(公告)日：2022-05-05

申请号：US17433714

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Qiuxu Zhuo ,  Anthony Luck

IPC: G06F3/06

Abstract: An apparatus for efficiently identifying and tracking cold memory pages. The apparatus includes a memory to store memory pages, one or more processor cores to access the memory pages stored in the memory by issuing access requests to the memory; and a page index bitmap to track accesses made by the one or more processor cores to the memory pages stored in the memory. The tracked accesses are usable to identify infrequently-accessed memory pages, wherein the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.

公开(公告)号：US11954356B2

公开(公告)日：2024-04-09

申请号：US17433714

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Qiuxu Zhuo ,  Anthony Luck

IPC: G06F3/06 ,  G06F12/0817 ,  G06F12/0868

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679 ,  G06F12/0817 ,  G06F12/0868

Abstract: Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US20240152281A1

公开(公告)日：2024-05-09

申请号：US18284266

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Qiuxu Zhuo ,  Anthony Luck

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0673 ,  G06F12/0607 ,  G06F2212/1032

Abstract: An embodiment of an integrated circuit may comprise first circuitry to manage a memory in accordance with a page size and a channel interleave granularity, and second circuitry coupled to the first circuitry, the second circuitry to store data in a primary region of the memory at a primary address, and manage a mirror of the data in a secondary region of the memory at a secondary address at a regional granularity on demand at run time. Other embodiments are disclosed and claimed.