公开(公告)号：US12278512B2

公开(公告)日：2025-04-15

申请号：US17132771

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jeffrey Schline ,  Samantha Rao ,  Naoki Matsumura ,  Ramon Cancel Olmo ,  Tod Schiff ,  Arunthathi Chandrabose

IPC: H02J7/00 ,  G06F1/3212 ,  G06F1/3287

Abstract: A workload dependent load-sharing mechanism in a multi-battery system. The mechanism is an energy management system that operates in three modes—energy saving mode, balancer mode, and turbo mode. The energy saving mode is a normal mode where the multiple batteries provide power to their own set of loads with least resistive dissipation. In balancing mode, the batteries are connected through switches operating in active mode so that the current shared is inversely proportion to the corresponding battery state-of-charge. In turbo mode, both batteries are connected in parallel through switches (e.g., on-switches) to provide maximum power to a processor or load. A controller optimizes the sequence and charging rate for a hybrid battery to maximize both the charging current and charging speed of the battery, while enabling longer battery life. The hybrid battery comprises a fast charging battery and a high-energy density battery.

公开(公告)号：US12242319B2

公开(公告)日：2025-03-04

申请号：US17482805

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan ,  Arunthathi Chandrabose

IPC: G06F1/26 ,  G06F1/3234 ,  H03F3/24

Abstract: An interface card includes a circuit board, a device mounted on the circuit board, and a PMIC mounted on the circuit board. The PMIC includes a PMIC processor communicatively coupled to a host processor of a host system. The PMIC processor is configured to receive an input voltage signal from a power supply that is external to the interface card. The PMIC processor generates at least one output voltage signal based on the input voltage signal. The at least one output voltage signal is supplied to the device. A power enable signal originating from the host processor is detected. The power enable signal is detected at a GPIO connector of the PMIC. The PMIC processor deactivates generation of the at least one output voltage signal based on the power enable signal.

公开(公告)号：US12250636B2

公开(公告)日：2025-03-11

申请号：US17520768

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan ,  Santhosh Ap ,  Arunthathi Chandrabose ,  Mythili Hegde

IPC: H04W52/02 ,  G06F1/26 ,  H04B7/0413 ,  H04W84/12

Abstract: A battery-powered device includes a baseband modem, configured to receive or send data according to a first operational mode, wherein the data correspond to a software application being executed on the battery-powered device; and a processor, configured to determine a resource requirement of the software application; and send a signal representing the determined resource requirement to the baseband modem; wherein the baseband modem is further configured to change from the first operational mode to a second operational mode based on the signal.

公开(公告)号：US20210135478A1

公开(公告)日：2021-05-06

申请号：US17132771

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jeffrey Schline ,  Samantha Rao ,  Naoki Matsumura ,  Ramon Cancel Olmo ,  Tod Schiff ,  Arunthathi Chandrabose

IPC: H02J7/00 ,  G06F1/3212 ,  G06F1/3287

Abstract: A workload dependent load-sharing mechanism in a multi-battery system. The mechanism is an energy management system that operates in three modes—energy saving mode, balancer mode, and turbo mode. The energy saving mode is a normal mode where the multiple batteries provide power to their own set of loads with least resistive dissipation. In balancing mode, the batteries are connected through switches operating in active mode so that the current shared is inversely proportion to the corresponding battery state-of-charge. In turbo mode, both batteries are connected in parallel through switches (e.g., on-switches) to provide maximum power to a processor or load. A controller optimizes the sequence and charging rate for a hybrid battery to maximize both the charging current and charging speed of the battery, while enabling longer battery life. The hybrid battery comprises a fast charging battery and a high-energy density battery.

公开(公告)号：US20230409099A1

公开(公告)日：2023-12-21

申请号：US17841246

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan ,  Arunthathi Chandrabose ,  Ratheesh Nair ,  Arvind Tomar

IPC: G06F1/30 ,  G06F3/14 ,  H02J9/06

CPC classification number: G06F1/30 ,  G06F3/1431 ,  H02J9/062 ,  H02J2310/58

Abstract: Systems, apparatuses and methods may provide for technology that configures a computing system to be a power sink from an external display, detects an alternating current (AC) power failure with respect to the external display, and configures the computing system to be a power source for the external display in response to the AC power failure. In one example, the technology places the external display in a low power state after the AC power failure is detected.

公开(公告)号：US20230273891A1

公开(公告)日：2023-08-31

申请号：US17680902

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Mythili Hegde ,  Shailendra Singh Chauhan ,  Arunthathi Chandrabose ,  Santhosh Ap ,  Shashi Kant Singh

IPC: G06F13/42 ,  G06F1/3234 ,  G06F1/3296

CPC classification number: G06F13/4221 ,  G06F1/3253 ,  G06F1/3296 ,  G06F2213/0026

Abstract: An apparatus comprises a circuit board comprising a connector in or on the circuit board. The apparatus is to be coupled to a bus via the connector. The apparatus comprises first circuitry to communicate with a processor via the connector and bus, second circuitry to detect a utilization state of the first circuitry, determine, based on the detected utilization state of the first circuitry, a level of current to be conducted with the connector; and generate a signal indicating of whether the level of current exceeds a threshold current capacity of the connector, and third circuitry to select a first operational mode from among multiple operational modes. The first circuitry is to operate in any of the multiple operational modes responsive to the third circuitry. Additional circuitry may be provided to identify a voltage level capability of the apparatus and to configure voltage level shifting circuitry connected to the bus.

公开(公告)号：US20230092240A1

公开(公告)日：2023-03-23

申请号：US17482805

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan ,  Arunthathi Chandrabose

IPC: G06F1/26 ,  H03F3/24 ,  G06F1/3234

Abstract: An interface card includes a circuit board, a device mounted on the circuit board, and a PMIC mounted on the circuit board. The PMIC includes a PMIC processor communicatively coupled to a host processor of a host system. The PMIC processor is configured to receive an input voltage signal from a power supply that is external to the interface card. The PMIC processor generates at least one output voltage signal based on the input voltage signal. The at least one output voltage signal is supplied to the device. A power enable signal originating from the host processor is detected. The power enable signal is detected at a GPIO connector of the PMIC. The PMIC processor deactivates generation of the at least one output voltage signal based on the power enable signal.