公开(公告)号：US20190101972A1

公开(公告)日：2019-04-04

申请号：US15721772

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Vasudev Bibikar ,  Aswin Ramachandran ,  Chin Seng Lu ,  Moorthy Rajesh ,  Darren S. Crews

IPC: G06F1/32 ,  G06F9/30

Abstract: A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.

公开(公告)号：US20170220099A1

公开(公告)日：2017-08-03

申请号：US15484361

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Aswin Ramachandran ,  Arvind Raman

IPC: G06F1/32 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/0724 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

公开(公告)号：US09625984B2

公开(公告)日：2017-04-18

申请号：US14671750

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Aswin Ramachandran ,  Arvind Raman

IPC: G06F1/26 ,  G06F1/32 ,  G06F11/07

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/0724 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

公开(公告)号：US10754413B2

公开(公告)日：2020-08-25

申请号：US15721772

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Vasudev Bibikar ,  Aswin Ramachandran ,  Chin Seng Lu ,  Moorthy Rajesh ,  Darren S. Crews

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30

Abstract: A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.

公开(公告)号：US10261572B2

公开(公告)日：2019-04-16

申请号：US15484361

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Aswin Ramachandran ,  Arvind Raman

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3228 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/07

Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.