公开(公告)号：US20230187441A1

公开(公告)日：2023-06-15

申请号：US17548027

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Sukru YEMENICIOGLU ,  Chanaka D. MUNASINGHE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0669 ,  H01L29/785

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure.

公开(公告)号：US20230290843A1

公开(公告)日：2023-09-14

申请号：US17693124

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Krishna GANESAN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/41783 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/413

Abstract: Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

公开(公告)号：US20200212039A1

公开(公告)日：2020-07-02

申请号：US16812726

申请日：2020-03-09

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20190006362A1

公开(公告)日：2019-01-03

申请号：US16103430

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20240429125A1

公开(公告)日：2024-12-26

申请号：US18212382

申请日：2023-06-21

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Shengsi LIU ,  Saurabh ACHARYA

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having deep via bar isolation are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes has a cut between first and second conductive structure portions. A cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.

公开(公告)号：US20230317595A1

公开(公告)日：2023-10-05

申请号：US17710817

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Makram ABD EL QADER ,  Tahir GHANI ,  Chanaka D. MUNASINGHE

IPC: H01L23/522 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L29/0673 ,  H01L27/0886 ,  H01L23/5283

Abstract: Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.

公开(公告)号：US20210175233A1

公开(公告)日：2021-06-10

申请号：US17183214

申请日：2021-02-23

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20190341383A1

公开(公告)日：2019-11-07

申请号：US16510688

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.