公开(公告)号：US20240203868A1

公开(公告)日：2024-06-20

申请号：US18066301

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  David Nathan Shykind ,  Richard E. Schenker ,  Florian Gstrein ,  Eungnak Han ,  Nafees Aminul Kabir ,  Sean Michael Pursel ,  Nityan Labros Nair ,  Robert Seidel

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76879

Abstract: Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.

公开(公告)号：US12266527B1

公开(公告)日：2025-04-01

申请号：US17559406

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Eungnak Han ,  Xuanxuan Chen ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein ,  David Nathan Shykind ,  Thomas Christopher Hoff

IPC: H01L21/027

Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

公开(公告)号：US12002678B2

公开(公告)日：2024-06-04

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20240249946A1

公开(公告)日：2024-07-25

申请号：US18625348

申请日：2024-04-03

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20220102148A1

公开(公告)日：2022-03-31

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.