公开(公告)号：US20240272547A1

公开(公告)日：2024-08-15

申请号：US18620187

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Charles Cameron Mokhtarzadeh ,  Sanjana Vijay Karpe ,  Scott B. Clendenning ,  James Munro Blackwell ,  Lauren Elizabeth Doyle ,  Brandon Jay Holybee

IPC: G03F7/004 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  H01L21/033

CPC classification number: G03F7/0042 ,  C23C16/407 ,  C23C16/45534 ,  C23C16/45553 ,  C23C16/56 ,  G03F7/161 ,  G03F7/162 ,  G03F7/2002 ,  G03F7/70033 ,  H01L21/0337

Abstract: Tin carboxylate precursors for metal oxide resist layers and related methods are disclosed herein. An example method of fabricating a semiconductor device disclosed herein includes synthesizing a precursor including tin, depositing a metal oxide resist layer on a base material by applying the precursor, the metal oxide resist layer including tin-6 clusters, and patterning the metal oxide resist layer.

公开(公告)号：US20220199462A1

公开(公告)日：2022-06-23

申请号：US17511693

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Florian Gstrein ,  Eungnak Han ,  Marie Krysak ,  Tayseer Mahdi ,  Xuanxuan Chen ,  Brandon Jay Holybee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

公开(公告)号：US12012473B2

公开(公告)日：2024-06-18

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: G03F7/11 ,  C08F265/02 ,  C08F265/04 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US20230200081A1

公开(公告)日：2023-06-22

申请号：US17557119

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  John J. Plombon ,  Dmitri E. Nikonov ,  Kevin P. O'Brien ,  Ian A. Young ,  Matthew V. Metz ,  Chia-Ching Lin ,  Scott B. Clendenning ,  Punyashloka Debashish ,  Carly Lorraine Rogan ,  Brandon Jay Holybee ,  Kaan Oguz

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Described herein are integrated circuit devices formed using perovskite materials. Perovskite materials with a similar crystal structure and different electrical properties can be layered to realize a transistor or memory device. In some embodiments, a ferroelectric perovskite can be incorporated into a device with other perovskite films to form a ferroelectric memory device.

公开(公告)号：US20220199540A1

公开(公告)日：2022-06-23

申请号：US17125232

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Marie Krysak ,  Brandon Jay Holybee ,  Florian Gstrein

IPC: H01L23/538

Abstract: Disclosed herein are guided vias in microelectronic structures. For example, a microelectronic structure may include a metallization layer including a conductive via in contact with a conductive line, wherein a center of a top surface of the conductive via is laterally offset from a center of a bottom surface of the conductive via.

公开(公告)号：US20210375745A1

公开(公告)日：2021-12-02

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: H01L23/528 ,  H01L23/522

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.