公开(公告)号：US20170147340A1

公开(公告)日：2017-05-25

申请号：US15396568

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F12/0897

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/384 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/125

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20230401037A1

公开(公告)日：2023-12-14

申请号：US18237859

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Erdinc OZTURK ,  Kirk S. YAP ,  Tomasz KANTECKI

IPC: G06F7/72

CPC classification number: G06F7/722 ,  G06F7/728

Abstract: Methods and apparatus for optimization techniques for modular multiplication algorithms. The optimization techniques may be applied to variants of modular multiplication algorithms, including variants of Montgomery multiplication algorithms and Barrett multiplication algorithms. The optimization techniques reduce the number of serial steps in Montgomery reduction and Barrett reduction. Modular multiplication operations involving products of integer inputs A and B may be performed in parallel to obtain a value C that is reduced to a residual RES. Modular multiplication and modular reduction operations may be performed in parallel. The number of serial steps in the modular reductions are reduced to L, where L serial steps, where w is a digit size in bits, and L is a number of digits of operands=[k/w].

公开(公告)号：US20170147343A1

公开(公告)日：2017-05-25

申请号：US15396578

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0897 ,  H04L9/06 ,  G06F12/1027 ,  G06F13/40 ,  G06F13/42 ,  G06F15/80 ,  G06F12/0875

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20170147342A1

公开(公告)日：2017-05-25

申请号：US15396576

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06 ,  G06F12/0897 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/28

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30156 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20170147341A1

公开(公告)日：2017-05-25

申请号：US15396574

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F15/80 ,  H04L9/06 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/0897

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20240028341A1

公开(公告)日：2024-01-25

申请号：US18375476

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Erdinc OZTURK ,  Kirk S. YAP ,  Tomasz KANTECKI

IPC: G06F9/38

CPC classification number: G06F9/3887 ,  G06F9/3877

Abstract: Examples described herein relate to a non-transitory computer-readable medium comprising instructions, that if executed by circuitry, cause the circuitry to: configure circuitry to perform cryptographic operations on packets based on Advanced Encryption Standard with Galois/Counter Mode (AES-GCM) hash (GHASH), wherein the cryptographic operations comprise a reduction operation and wherein the reduction operation comprises a single Galois territory multiplication 64 bit operation. The circuitry can include one or more of: a central processing unit (CPU), CPU-executed microcode, an accelerator, or a network interface device.

公开(公告)号：US20190332378A1

公开(公告)日：2019-10-31

申请号：US16450319

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027 ,  G06F12/0875 ,  H04L9/06 ,  G06F15/80 ,  H04L9/32 ,  G09C1/00 ,  G06F13/42 ,  G06F13/40 ,  G06F13/28 ,  G06F21/60 ,  G06F12/0897

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20170147348A1

公开(公告)日：2017-05-25

申请号：US15396563

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  H04L9/06 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30156 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20170109162A1

公开(公告)日：2017-04-20

申请号：US15396572

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027 ,  G06F12/0875 ,  G06F12/0897 ,  H04L9/06 ,  G06F15/80

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30156 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.