公开(公告)号：US09418000B2

公开(公告)日：2016-08-16

申请号：US14579971

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Shyam Sunder Raghunathan ,  Iwen Chao ,  Xin Guo ,  Pranav Kalavade ,  Krishna K. Parat ,  Feng Zhu

IPC: G11C16/04 ,  G06F12/02 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G06F11/10 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F11/1084 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现动态存储器管理的装置，系统和方法。 在一个示例中，控制器包括用于监视非易失性存储器的至少一个性能参数的逻辑，确定何时至少一个性能参数通过指示非易失性存储器性能下降的阈值，以及响应于该至少一个 性能参数通过阈值，以修改非易失性存储器的至少一个操作属性。 还公开并要求保护其他实例。

公开(公告)号：US09524774B2

公开(公告)日：2016-12-20

申请号：US14954002

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G11C11/56 ,  G11C16/34 ,  G06F12/02

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

公开(公告)号：US20160155497A1

公开(公告)日：2016-06-02

申请号：US14954002

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Abstract translation: 电子存储器或控制器可以使用第一类型的读取命令，寻址到电子存储器的存储器的第一页，其包括用于指示电子存储器的第二页存储器尚未被编程的信息和第二类型的读取 命令，寻址到存储器的第一页，其包括用于指示第二页存储器已被编程的信息。 存储器的第一页可以包括多级单元（MLC）的下页，并且第二页存储器可以包括相同MLC的上页。 在使用第一种类型的读取命令的时间段内启用第二页内存。

公开(公告)号：US09236136B2

公开(公告)日：2016-01-12

申请号：US13714763

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G06F12/02 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Abstract translation: 电子存储器或控制器可以使用第一类型的读取命令，寻址到电子存储器的存储器的第一页，其包括用于指示电子存储器的第二页存储器尚未被编程的信息和第二类型的读取 命令，寻址到存储器的第一页，其包括用于指示第二页存储器已被编程的信息。 存储器的第一页可以包括多级单元（MLC）的下页，并且第二页存储器可以包括相同MLC的上页。 在使用第一种类型的读取命令的时间段内启用第二页内存。

公开(公告)号：US09543019B2

公开(公告)日：2017-01-10

申请号：US13710913

申请日：2012-12-11

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G06F11/10 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G06F11/1048 ,  G11C11/5628

Abstract: Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.

Abstract translation: 方法，设备和制造品可以接收第一页数据并且校正第一页数据中的一个或多个错误以产生校正数据的页面。 然后可以用第二页数据和校正数据的页面发送程序命令，以编程存储器页面以存储第二页数据。