公开(公告)号：US11916003B2

公开(公告)日：2024-02-27

申请号：US16575307

申请日：2019-09-18

申请人： Intel Corporation

发明人： Xiao Lu ,  Jiongxin Lu ,  Christopher Combs ,  Alexander Huettis ,  John Harper ,  Jieping Zhang ,  Nachiket R. Raravikar ,  Pramod Malatkar ,  Steven A. Klein ,  Carl Deppisch ,  Mohit Sood

IPC分类号： H01L23/48 ,  B23K3/06 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/49833 ,  B23K3/0623 ,  H01L23/49822 ,  H01L23/4985 ,  H01L23/5387

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

公开(公告)号：US20220102234A1

公开(公告)日：2022-03-31

申请号：US17033080

申请日：2020-09-25

申请人： Intel Corporation

发明人： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC分类号： H01L23/36 ,  H01L23/488 ,  H01L23/00 ,  H01L21/50 ,  H01L21/768

摘要： An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US12040246B2

公开(公告)日：2024-07-16

申请号：US17033080

申请日：2020-09-25

申请人： Intel Corporation

发明人： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488 ,  H01L21/60

CPC分类号： H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

摘要： An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US20240332112A1

公开(公告)日：2024-10-03

申请号：US18744108

申请日：2024-06-14

申请人： Intel Corporation

发明人： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC分类号： H01L23/36 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488

CPC分类号： H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

摘要： An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US20220285288A1

公开(公告)日：2022-09-08

申请号：US17192770

申请日：2021-03-04

申请人： Intel Corporation

发明人： Valery Ouvarov-Bancalero ,  John Harper ,  Malavarayan Sankarasubramanian ,  Patrick Nardi ,  Bamidele Daniel Falola ,  Ravi Siddappa ,  James Mertens

IPC分类号： H01L23/00 ,  H01L23/06 ,  H05K7/14

摘要： A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an “anti-invar” metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa.