公开(公告)号：US20190355411A1

公开(公告)日：2019-11-21

申请号：US15980813

申请日：2018-05-16

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Kaushik Vaidyanathan ,  Anant Nori ,  Sreenivas Subramoney ,  Tanay Karnik

IPC: G11C11/4094 ,  G11C11/4091 ,  G11C11/4093 ,  G06F13/16

Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

公开(公告)号：US10176124B2

公开(公告)日：2019-01-08

申请号：US15477069

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sriseshan Srikanth ,  Lavanya Subramanian ,  Sreenivas Subramoney

IPC: G06F13/16 ,  G06F13/40 ,  G06F9/38 ,  G11C7/10 ,  G11C7/22

Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.

公开(公告)号：US10191689B2

公开(公告)日：2019-01-29

申请号：US15393998

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sriseshan Srikanth ,  Lavanya Subramanian ,  Sreenivas Subramoney

IPC: G06F3/06

Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.

公开(公告)号：US20180188994A1

公开(公告)日：2018-07-05

申请号：US15393998

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sriseshan Srikanth ,  Lavanya Subramanian ,  Sreenivas Subramoney

IPC: G06F3/06

CPC classification number: G06F12/00

Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.

公开(公告)号：US20200285580A1

公开(公告)日：2020-09-10

申请号：US16618070

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Sreenivas Subramoney ,  Anant Vithal Nori

IPC: G06F12/0842 ,  G11C11/406 ,  G11C11/4096

Abstract: In one embodiment, an apparatus comprises a processor and a memory controller. The processor is to identify a memory access operation associated with a memory location of a memory. The processor is further to determine that a cache memory does not contain data associated with the memory location. The processor is further to send a memory access notification to a memory controller via a first transmission path. The processor is further to send a memory access request to the memory controller via a second transmission path, wherein the second transmission path is slower than the first transmission path. The memory controller is to receive the memory access notification via the first transmission path, and send a memory activation request based on the memory access notification, wherein the memory activation request comprises a request to activate a memory bank associated with the memory location.

公开(公告)号：US20180285286A1

公开(公告)日：2018-10-04

申请号：US15477069

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sriseshan Srikanth ,  Lavanya Subramanian ,  Sreenivas Subramoney

IPC: G06F13/16 ,  G06F13/40 ,  G06F9/38 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F13/161 ,  G06F9/3838 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4059 ,  G11C7/1072 ,  G11C7/22

Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.

公开(公告)号：US20180088944A1

公开(公告)日：2018-03-29

申请号：US15275066

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Sreenivas Subramoney ,  Nithiyanandan Bashyam ,  Anant Nori

IPC: G06F9/30 ,  G06F12/0862 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/3009 ,  G06F9/30047 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

公开(公告)号：US11734174B2

公开(公告)日：2023-08-22

申请号：US16576687

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Tejpal Singh ,  Yen-Cheng Liu ,  Lavanya Subramanian ,  Mahesh Kumashikar ,  Sri Harsha Choday ,  Sreenivas Subramoney ,  Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0806 ,  G06F11/20

CPC classification number: G06F12/0804 ,  G06F11/2089 ,  G06F12/0806 ,  G06F12/0866

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

公开(公告)号：US20210089448A1

公开(公告)日：2021-03-25

申请号：US16576687

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Tejpal Singh ,  Yen-Cheng Liu ,  Lavanya Subramanian ,  Mahesh Kumashikar ,  Sri Harsha Chodav ,  Sreenivas Subramoney ,  Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G06F12/0804 ,  G06F11/20 ,  G06F12/0806 ,  G06F12/0866

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

公开(公告)号：US10559348B2

公开(公告)日：2020-02-11

申请号：US15980813

申请日：2018-05-16

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Kaushik Vaidyanathan ,  Anant Nori ,  Sreenivas Subramoney ,  Tanay Karnik

IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/16 ,  G11C11/4093 ,  G11C11/4091

Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.