公开(公告)号：US20230101378A1

公开(公告)日：2023-03-30

申请号：US17448738

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Joachim ASSENMACHER ,  Walther LUTZ ,  Martin OSTERMAYR ,  Georg SEIDEMANN

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/532 ,  H01L49/02

Abstract: A semiconductor die is disclosed, including a plurality of transistors at a frontside of a semiconductor substrate, a backside inductor at a backside of the semiconductor substrate; and a frontside inductor at the frontside of the semiconductor substrate. The frontside inductor and the backside inductor are inductively coupled.

公开(公告)号：US20230095162A1

公开(公告)日：2023-03-30

申请号：US17448714

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Martin OSTERMAYR ,  Walther LUTZ ,  Joachim ASSENMACHER

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device is provided. The semiconductor device comprises a semiconductor die comprising a semiconductor substrate and a plurality of transistors arranged at a front side of the semiconductor substrate. Further, the semiconductor die comprises a first electrically conductive structure extending from the front side of the semiconductor substrate to a backside of the semiconductor substrate and a second electrically conductive structure extending from the front side of the semiconductor substrate to the backside of the semiconductor substrate. The semiconductor device further comprises an interposer directly attached to the backside of the semiconductor substrate. The interposer comprises a first trace electrically connected to the first electrically conductive structure of the semiconductor die. Further the interposer comprises the first trace or a second trace electrically connected to the second electrically conductive structure of the semiconductor die.

公开(公告)号：US20230197537A1

公开(公告)日：2023-06-22

申请号：US17644801

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard GEIGER ,  Klaus HEROLD ,  Harald GOSSNER ,  Martin OSTERMAYR ,  Georgios PANAGOPOULOS ,  Johannes RAUH ,  Joachim SINGER ,  Thomas WAGNER

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L22/32 ,  H01L23/481

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

公开(公告)号：US20230103023A1

公开(公告)日：2023-03-30

申请号：US17448716

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Martin OSTERMAYR ,  Joachim SINGER ,  Klaus HEROLD

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor die is provided. The semiconductor die comprises a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure. A top surface of the electrically conductive structure is contacted at the front side of the semiconductor substrate and a bottom surface of the electrically conductive structure is contacted at a backside of the semiconductor substrate. Further, the semiconductor die comprises a backside metallization layer stack attached to the backside of the semiconductor substrate. A first portion of a wiring structure is formed in a first metallization layer of the backside metallization layer stack and a second portion of the wiring structure is formed in a second metallization layer of the backside metallization layer stack. Further, a tapered vertical connection is formed between the first portion of the wiring structure and the second portion of the wiring structure, wherein the first metallization layer is closer to the semiconductor substrate than the second metallization layer. A width of the tapered vertical connection increases towards the first metallization layer.

公开(公告)号：US20230102133A1

公开(公告)日：2023-03-30

申请号：US17448734

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Martin OSTERMAYR ,  Walther LUTZ ,  Joachim ASSENMACHER ,  Georg SEIDEMANN

IPC: H01L23/64 ,  H01L23/00

Abstract: A semiconductor die is disclosed, including circuitry comprising a transistor at a frontside of a semiconductor substrate, and a backside inductor at a backside of the semiconductor substrate. The backside inductor is electrically connected to the transistor of the circuitry.