中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.017 seconds)

    Arsenic-doped epitaxial, source/drain regions for NMOS
    1.
    发明授权
    Arsenic-doped epitaxial, source/drain regions for NMOS 有权

    公开(公告)号：US11610889B2

    公开(公告)日：2023-03-21

    申请号：US16145375

    申请日：2018-09-28

    Applicant: INTEL CORPORATION

    Inventor： Anand Murthy ,  Ryan Keech ,  Nicholas G. Minutillo ,  Ritesh Jhaveri

    IPC: H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

    Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

    Transistors with high density channel semiconductor over dielectric material
    3.
    发明授权
    Transistors with high density channel semiconductor over dielectric material 有权

    公开(公告)号：US11557658B2

    公开(公告)日：2023-01-17

    申请号：US16649592

    申请日：2017-12-27

    Applicant: INTEL CORPORATION

    Inventor： Gilbert Dewey ,  Sean T. Ma ,  Tahir Ghani ,  Willy Rachmady ,  Cheng-Ying Huang ,  Anand S. Murthy ,  Harold W. Kennel ,  Nicholas G. Minutillo ,  Matthew V. Metz

    IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

    Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.

    Source or drain structures with phosphorous and arsenic co-dopants
    4.
    发明授权
    Source or drain structures with phosphorous and arsenic co-dopants 有权

    公开(公告)号：US11552169B2

    公开(公告)日：2023-01-10

    申请号：US16367134

    申请日：2019-03-27

    Applicant: Intel Corporation

    Inventor： Anand Murthy ,  Ryan Keech ,  Nicholas G. Minutillo ,  Suresh Vishwanath

    IPC: H01L29/78 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08

    Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

    Channel layer formed in an art trench
    5.
    发明授权
    Channel layer formed in an art trench 有权

    公开(公告)号：US11164974B2

    公开(公告)日：2021-11-02

    申请号：US16631363

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Nancy Zelick ,  Harold Kennel ,  Nicholas G. Minutillo ,  Cheng-Ying Huang

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/201 ,  H01L21/8234 ,  H01L27/088

    Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

    IMPROVED CHANNEL LAYER FORMED IN AN ART TRENCH
    7.
    发明申请
    IMPROVED CHANNEL LAYER FORMED IN AN ART TRENCH 审中-公开

    公开(公告)号：US20200220017A1

    公开(公告)日：2020-07-09

    申请号：US16631363

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Nancy Zelick ,  Harold Kennel ,  Nicholas G. Minutillo ,  Cheng-Ying Huang

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

    Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

    Transistor with isolation below source and drain
    8.
    发明授权
    Transistor with isolation below source and drain 有权

    公开(公告)号：US12288803B2

    公开(公告)日：2025-04-29

    申请号：US18540544

    申请日：2023-12-14

    Applicant: Intel Corporation

    Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

    IPC: H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

    Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Patent Agency Ranking