公开(公告)号：US11462568B2

公开(公告)日：2022-10-04

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Justin Weber ,  Harold Kennel ,  Willy Rachmady ,  Gilbert Dewey ,  Van H. Le ,  Abhishek Sharma ,  Patrick Morrow ,  Ashish Agrawal

IPC: H01L27/12 ,  H01L21/8256 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11973143B2

公开(公告)日：2024-04-30

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Benjamin Chu-Kung ,  Subrina Rafique ,  Devin Merrill ,  Ashish Agrawal ,  Harold Kennel ,  Yang Cao ,  Dipanjan Basu ,  Jessica Torres ,  Anand Murthy

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US11929435B2

公开(公告)日：2024-03-12

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/2003 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US11508577B2

公开(公告)日：2022-11-22

申请号：US16024694

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L29/78 ,  H01L27/12

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

公开(公告)号：US11367789B2

公开(公告)日：2022-06-21

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Sean T. Ma ,  Harold Kennel

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/778 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US20200098753A1

公开(公告)日：2020-03-26

申请号：US16141000

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/267 ,  H01L29/10 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US12255234B2

公开(公告)日：2025-03-18

申请号：US18409509

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US11923421B2

公开(公告)日：2024-03-05

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

CPC classification number: H01L29/165 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US11798991B2

公开(公告)日：2023-10-24

申请号：US16457690

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Rishabh Mehandru ,  Willy Rachmady ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02356 ,  H01L21/02592 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871

Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.

公开(公告)号：US11637185B2

公开(公告)日：2023-04-25

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin Weber ,  Harold Kennel ,  Abhishek Sharma ,  Christopher Jezewski ,  Matthew V. Metz ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Van H. Le ,  Arnab Sen Gupta

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L21/322 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L29/267

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.