中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.013 seconds)

    PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY
    1.
    发明申请
    PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY 审中-公开
    在非易失性随机存取存储器中提供保持电流

    公开(公告)号：US20170053698A1

    公开(公告)日：2017-02-23

    申请号：US15347736

    申请日：2016-11-09

    Applicant: Intel Corporation

    Inventor： Dany-Sebastien Ly-Gagnon ,  Kiran Pangal ,  Raymond W. Zeng ,  Mase J. Taub

    IPC: G11C13/00

    CPC classification number: G11C11/00 ,  G06F11/1048 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L29/06 ,  H04L65/403

    Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。

    PHASE CHANGE MEMORY CURRENT
    2.
    发明申请
    PHASE CHANGE MEMORY CURRENT 有权
    相变记忆电流

    公开(公告)号：US20160351258A1

    公开(公告)日：2016-12-01

    申请号：US14725826

    申请日：2015-05-29

    Applicant: Intel Corporation

    Inventor： Mase J. Taub ,  Sandeep K. Guliani ,  Kiran Pangal ,  Raymond W. Zeng

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/79

    Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

    Abstract translation: 本公开涉及相变存储器电流。 一种装置包括一个包括字线（WL）控制模块和位线（BL）控制模块的存储器控​​制器，该存储器控制器开始选择一个存储单元。 该装置还包括缓解模块，用于配置第一线路选择逻辑以减少存储器单元的瞬态能量耗散，与选择存储器单元有关的瞬态能量。

    CELL PROGRAMMING VERIFICATION
    4.
    发明申请
    CELL PROGRAMMING VERIFICATION 审中-公开

    公开(公告)号：US20180068720A1

    公开(公告)日：2018-03-08

    申请号：US15690148

    申请日：2017-08-29

    Applicant: Intel Corporation

    Inventor： Daniel J. Chu ,  Raymond W. Zeng ,  Doyle Rivers

    IPC: G11C13/00

    CPC classification number: G11C13/0004 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069

    Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

    Cross point memory control
    5.
    发明授权
    Cross point memory control 有权

    公开(公告)号：US10546634B2

    公开(公告)日：2020-01-28

    申请号：US16140441

    申请日：2018-09-24

    Applicant: Intel Corporation

    Inventor： Raymond W. Zeng ,  Mase J. Taub ,  Kiran Pangal ,  Sandeep K. Guliani

    IPC: G11C13/00 ,  G11C8/06 ,  G11C16/08 ,  G11C16/34

    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

    Cross point memory control
    6.
    发明授权
    Cross point memory control 有权

    公开(公告)号：US10134468B2

    公开(公告)日：2018-11-20

    申请号：US15465470

    申请日：2017-03-21

    Applicant: Intel Corporation

    Inventor： Raymond W. Zeng ,  Mase J. Taub ,  Kiran Pangal ,  Sandeep K. Guliani

    IPC: G11C13/00

    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

    Provision of holding current in non-volatile random access memory
    8.
    发明授权
    Provision of holding current in non-volatile random access memory 有权
    在非易失性随机存取存储器中提供保持电流

    公开(公告)号：US09543004B1

    公开(公告)日：2017-01-10

    申请号：US14742316

    申请日：2015-06-17

    Applicant: Intel Corporation

    Inventor： Dany-Sebastien Ly-Gagnon ,  Kiran Pangal ,  Raymond W. Zeng ,  Mase J. Taub

    IPC: G11C13/00 ,  G06F11/10 ,  G11C7/04 ,  G11C11/56 ,  H04L29/06

    CPC classification number: G11C11/00 ,  G06F11/1048 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L29/06 ,  H04L65/403

    Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。

    Cell programming verification
    9.
    发明授权
    Cell programming verification 有权

    公开(公告)号：US10325652B2

    公开(公告)日：2019-06-18

    申请号：US15690148

    申请日：2017-08-29

    Applicant: Intel Corporation

    Inventor： Daniel J. Chu ,  Raymond W. Zeng ,  Doyle Rivers

    IPC: G11C13/00

    Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

Patent Agency Ranking