公开(公告)号：US09891695B2

公开(公告)日：2018-02-13

申请号：US14751889

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ariel Berkovits ,  Michael Mishaeli ,  Nadav Shulman ,  Sameer Desai ,  Shani Rehana ,  Ittai Anati ,  Hisham Shafi

IPC: G06F1/32 ,  G06F12/08 ,  G06F12/14 ,  G06F12/0868 ,  G06F12/0804 ,  G06F12/0888

CPC classification number: G06F1/3287 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/1433 ,  G06F2212/1052 ,  G06F2212/311 ,  G06F2212/621

Abstract: A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.

公开(公告)号：US20170149554A1

公开(公告)日：2017-05-25

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US09535476B2

公开(公告)日：2017-01-03

申请号：US14497549

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Shani Rehana ,  Alexander Gendler ,  Larisa Novakovsky

IPC: G06F1/12 ,  G06F3/06 ,  G06F5/06 ,  G06F1/26 ,  G06F5/10

CPC classification number: G06F1/26 ,  G06F1/12 ,  G06F3/0656 ,  G06F5/10 ,  G06F15/17331

Abstract: In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括根据第一时钟进行操作的第一域。 第一域包括首先在先出缓冲器（有效载荷BGF）中存储数据分组的写入源，有效负载气泡生成器，以及写入信用逻辑以维持写入信用的计数。 处理器还包括第二域，以便按照第二时钟进行操作。 当写入源具有在第二时钟关闭时要存储的数据包时，写入源将数据包写入有效载荷BGF，响应于至少一个写入信用的计数，并且在第二个时钟为 重新启动第二个域是从有效载荷BGF读取数据包。 描述和要求保护其他实施例。

公开(公告)号：US09660799B1

公开(公告)日：2017-05-23

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: G06F1/06 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US20160378660A1

公开(公告)日：2016-12-29

申请号：US14751889

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ariel Berkovits ,  Michael Mishaeli ,  Nadav Shulman ,  Sameer Desai ,  Shani Rehana ,  Ittai Anati ,  Hisham Shafi

IPC: G06F12/08 ,  G11C11/406 ,  G06F1/32 ,  G11C7/10

CPC classification number: G06F1/3287 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/1433 ,  G06F2212/1052 ,  G06F2212/311 ,  G06F2212/621

Abstract: A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.

Abstract translation: 描述了分别将外部存储器和/或从外部存储器内核心存储器内容清理和恢复的方法和装置。 在一个实施例中，该装置是包括多个处理器核心的集成电路，所述多个处理核心包括一个核心，其具有可操作以存储一个核心数据的第一存储器，所述一个核心将数据从第一存储器存储到 响应于接收到一个核心将从第一低功率空闲状态转换到第二低功率空闲状态的第一指示，并且接收到从一个核心外部产生的第二指示，该第二存储器位于处理器的外部，指示该 一个核心是将数据从第一存储器存储到第二存储器，存储数据的第二存储器中的位置可由一个核心访问，并且IC中的其他处理器核心不可访问; 以及耦合到所述多个核心并位于所述多个核心外部的电力管理控制器。