公开(公告)号：US20220310901A1

公开(公告)日：2022-09-29

申请号：US17211736

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Tanay GOSAVI ,  Emily WALKER ,  Chia-Ching LIN ,  Ian A. YOUNG

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10

Abstract: Spin orbit torque (SOT) devices with topological insulator (TI) and heavy metal insert are described. In an example, an integrated circuit structure includes a spin orbit coupling (SOC) interconnect including a TI material. A magnetic layer is above the SOC interconnect. An insert layer includes a heavy metal between and in contact with the TI material and the magnetic layer.

公开(公告)号：US20200313076A1

公开(公告)日：2020-10-01

申请号：US16367131

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Christopher WIEGAND ,  Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI

IPC: H01L43/02 ,  H01L43/10 ,  H01F10/32 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

Abstract: A spin orbit memory device includes a first electrode including a beta-phase material. The spin orbit memory device further includes a material layer stack on a portion of the first electrode. The material layer stack includes a first layer on the first electrode, where the first layer includes a bcc material such as molybdenum. The material layer stack further includes layers of a perpendicular magnetic tunnel junction (pMTJ) device on the first layer. The pMTJ device includes a free magnet structure on the first layer, where the free magnet structure includes a first magnet and a second magnet on the first magnet. The pMTJ device further includes a fixed magnet above the free magnet structure and a tunnel barrier layer between the magnet structure and the third magnet and a second electrode coupled with the second magnet.

公开(公告)号：US20200006643A1

公开(公告)日：2020-01-02

申请号：US16024712

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Gary ALLEN ,  Scott B. CLENDENING ,  Ian YOUNG

IPC: H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H01L27/22

Abstract: Embodiments herein relate to manufacturing a magnetic random access memory (MRAM). In particular, a process may include coupling a side of a magnetic free layer of a magnetic tunnel junction (MTJ) to a first side of a hybrid spin orbit torque (SOT) electrode-insert layer, coupling a first side of an atomic layer etching (ALE) etch layer to a second side of the hybrid SOT electrode-insert layer opposite the first side, applying an interlayer dielectric (ILD) layer to edges of the MTJ, the SOT electrode and the etch layers, the ILD layer in a plane substantially perpendicular to a plane of the MTJ, SOT electrode and ALE etch layers, and etching the ALE etch layer using ALE until the SOT layer is exposed.

公开(公告)号：US20210408288A1

公开(公告)日：2021-12-30

申请号：US16913835

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20200212055A1

公开(公告)日：2020-07-02

申请号：US16236047

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Dmitri NIKONOV ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: H01L27/11507

Abstract: A memory device comprises a trench within an insulating layer. A bottom electrode material is along sidewalls and a bottom of the trench, the bottom electrode material conformal to a top surface of the insulating layer. A ferroelectric material is conformal to the bottom electrode. A top electrode material is conformal to the ferroelectric material, wherein the bottom electrode material, the ferroelectric material and the top electrode material all extend above and across the top surface of the insulating layer.

公开(公告)号：US20200006636A1

公开(公告)日：2020-01-02

申请号：US16024709

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Gary ALLEN ,  Kaan OGUZ ,  Kevin O?BRIEN ,  Noriyuki SATO ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

公开(公告)号：US20220199799A1

公开(公告)日：2022-06-23

申请号：US17131706

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Chelsey DOROW ,  Carl NAYLOR ,  Kirby MAXEY ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Ashish Verma PENUMATCHA ,  Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Sudarat LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Thin film transistors having boron nitride integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first gate stack above a substrate. A 2D channel material layer is above the first gate stack. A second gate stack is above the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack and in contact with the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack and in contact with the 2D channel material layer. A hexagonal boron nitride (hBN) layer is included between the first gate stack and the 2D channel material layer, between the second gate stack and the 2D channel material layer, or both.

公开(公告)号：US20210391478A1

公开(公告)日：2021-12-16

申请号：US16902069

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Carl NAYLOR ,  Ashish Verma PENUMATCHA ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.

公开(公告)号：US20200006637A1

公开(公告)日：2020-01-02

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Christopher WIEGAND ,  Angeline SMITH ,  Noriyuki SATO ,  Kevin O'BRIEN ,  Benjamin BUFORD ,  Ian YOUNG ,  MD Tofizur RAHMAN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20200006627A1

公开(公告)日：2020-01-02

申请号：US16022519

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12

Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.