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    Retention optimized memory device using predictive data inversion
    2.
    发明申请
    Retention optimized memory device using predictive data inversion 有权
    使用预测数据反演的保留优化的存储器件

    公开(公告)号：US20150213847A1

    公开(公告)日：2015-07-30

    申请号：US14683687

    申请日：2015-04-10

    Applicant: Invensas Corporation

    Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

    IPC: G11C7/00

    CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

    Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

    Abstract translation: 一种存储数据的方法。 该方法包括提供包括存储器空间的可寻址存储器，其中存储器空间包括多个存储器单元。 该方法包括配置可寻址存储器，使得当将一个或多个外部数据状态的第一外部数据状态写入存储器空间时，存储器空间中的多个存储器单元的大部分将内部数据值存储在优选偏置条件中， 其中所述第一外部数据状态与优选偏置条件相反。

    DRAM adjacent row disturb mitigation
    5.
    发明授权
    DRAM adjacent row disturb mitigation 有权

    公开(公告)号：US09812185B2

    公开(公告)日：2017-11-07

    申请号：US15019788

    申请日：2016-02-09

    Applicant: Invensas Corporation

    Inventor： David Edward Fisch ,  William C. Plants

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/406 ,  G11C11/40626 ,  G11C11/4087 ,  G11C29/025 ,  G11C29/06 ,  G11C29/789 ,  G11C2029/0403

    Abstract: The invention pertains to data disturb vulnerabilities in Dynamic Random Access Memory (DRAM) integrated circuits. In particular, it pertains to mitigating attacks on a computational system by deliberate inducement of disturbs on a targeted row (also known as “row hammering”) in the system's DRAM memory. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate. When a tracked address poses a danger of causing a memory disturb, each row adjacent to the tracked address row is refreshed thus mitigating the danger.

    DRAM adjacent row disturb mitigation
    10.
    发明授权
    DRAM adjacent row disturb mitigation 有权

    公开(公告)号：US10262717B2

    公开(公告)日：2019-04-16

    申请号：US15803710

    申请日：2017-11-03

    Applicant: Invensas Corporation

    Inventor： David Edward Fisch ,  William C. Plants

    IPC: G11C11/406 ,  G11C11/408 ,  G11C29/02 ,  G11C29/06 ,  G11C29/00 ,  G11C29/04

    Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.

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