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    LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME
    4.
    发明申请
    LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME 有权
    闪存存储器件的本地自动提升方法和使用其的程序方法

    公开(公告)号：US20110103154A1

    公开(公告)日：2011-05-05

    申请号：US12917634

    申请日：2010-11-02

    申请人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

    发明人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

    IPC分类号： G11C16/12 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/3418

    摘要： Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.

    摘要翻译： 提供了一种闪存器件的局部自增强方法，其包括至少一个具有分别连接到字线的存储单元的串。 局部自增强方法包括在串的通道处形成势阱，并在势阱处形成位于所选存储单元的通道两侧的电势壁。 所选择的存储单元的通道在局部受到潜在的壁限制，并且当将程序电压施加到所选择的存储单元时升压。

    Local self-boosting method of flash memory device and program method using the same
    6.
    发明授权
    Local self-boosting method of flash memory device and program method using the same 有权
    闪存器件的局部自增强方法及使用其的程序方法

    公开(公告)号：US08625357B2

    公开(公告)日：2014-01-07

    申请号：US12917634

    申请日：2010-11-02

    申请人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

    发明人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C16/3418

    摘要： Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.

    摘要翻译： 提供了一种闪存器件的局部自增强方法，其包括至少一个具有分别连接到字线的存储单元的串。 局部自增强方法包括在串的通道处形成势阱，并在势阱处形成位于所选存储单元的通道两侧的电势壁。 所选择的存储单元的通道在局部受到潜在的壁限制，并且当将程序电压施加到所选择的存储单元时升压。

    Non-Volatile Memory Devices Having Semiconductor Barrier Patterns and Methods of Forming Such Devices
    7.
    发明申请
    Non-Volatile Memory Devices Having Semiconductor Barrier Patterns and Methods of Forming Such Devices 审中-公开
    具有半导体阻挡图案的非易失性存储器件和形成这种器件的方法

    公开(公告)号：US20110073928A1

    公开(公告)日：2011-03-31

    申请号：US12894844

    申请日：2010-09-30

    申请人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    发明人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7881

    摘要： Provided are a non-volatile memory device and a method of forming the same. The non-volatile memory device includes: a tunnel insulation layer on a substrate; a floating gate on the tunnel insulation layer; a blocking insulation layer on the floating gate; a first barrier pattern, between the top of the floating gate and the blocking insulation layer, having a higher conduction band energy level than the floating gate; and a control gate on the blocking insulation layer.

    摘要翻译： 提供一种非易失性存储器件及其形成方法。 非易失性存储器件包括：衬底上的隧道绝缘层; 隧道绝缘层上的浮栅; 浮栅上的阻挡绝缘层; 在浮置栅极的顶部和阻挡绝缘层之间的第一阻挡图案具有比浮动栅极更高的导带能级; 和阻挡绝缘层上的控制栅极。

    Non-volatile memory devices and methods of manufacturing the same
    8.
    发明授权
    Non-volatile memory devices and methods of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08368138B2

    公开(公告)日：2013-02-05

    申请号：US12884668

    申请日：2010-09-17

    申请人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    发明人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336

    摘要： Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.

    摘要翻译： 半导体器件及其形成方法。 半导体器件包括在衬底上的隧道绝缘层，隧道绝缘层上的浮动栅极，浮置栅极上的栅极绝缘层，浮动栅极的顶部和第二栅极之间的低介电常数（低k）区域 栅极绝缘层，具有比氧化硅更低的介电常数的低k区域以及栅极绝缘层上的控制栅极。

    Semiconductor devices and methods of fabricating the same
    9.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08587052B2

    公开(公告)日：2013-11-19

    申请号：US13402171

    申请日：2012-02-22

    申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

    摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

    摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130032875A1

    公开(公告)日：2013-02-07

    申请号：US13402171

    申请日：2012-02-22

    申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    IPC分类号： H01L29/792 ,  H01L29/78

    CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

    摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

    摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。