公开(公告)号：US08791520B2

公开(公告)日：2014-07-29

申请号：US12986553

申请日：2011-01-07

申请人： Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

发明人： Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

摘要翻译： 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US20110073928A1

公开(公告)日：2011-03-31

申请号：US12894844

申请日：2010-09-30

申请人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

发明人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7881

摘要： Provided are a non-volatile memory device and a method of forming the same. The non-volatile memory device includes: a tunnel insulation layer on a substrate; a floating gate on the tunnel insulation layer; a blocking insulation layer on the floating gate; a first barrier pattern, between the top of the floating gate and the blocking insulation layer, having a higher conduction band energy level than the floating gate; and a control gate on the blocking insulation layer.

摘要翻译： 提供一种非易失性存储器件及其形成方法。 非易失性存储器件包括：衬底上的隧道绝缘层; 隧道绝缘层上的浮栅; 浮栅上的阻挡绝缘层; 在浮置栅极的顶部和阻挡绝缘层之间的第一阻挡图案具有比浮动栅极更高的导带能级; 和阻挡绝缘层上的控制栅极。

公开(公告)号：US08368138B2

公开(公告)日：2013-02-05

申请号：US12884668

申请日：2010-09-17

申请人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

发明人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336

摘要： Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.

摘要翻译： 半导体器件及其形成方法。 半导体器件包括在衬底上的隧道绝缘层，隧道绝缘层上的浮动栅极，浮置栅极上的栅极绝缘层，浮动栅极的顶部和第二栅极之间的低介电常数（低k）区域 栅极绝缘层，具有比氧化硅更低的介电常数的低k区域以及栅极绝缘层上的控制栅极。

公开(公告)号：US09601204B2

公开(公告)日：2017-03-21

申请号：US14523977

申请日：2014-10-27

申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： G11C5/02 ,  G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L27/11573 ,  G11C5/02 ,  G11C5/025 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

公开(公告)号：US20110079839A1

公开(公告)日：2011-04-07

申请号：US12894863

申请日：2010-09-30

申请人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

发明人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

摘要： Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

摘要翻译： 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

公开(公告)号：US09362303B2

公开(公告)日：2016-06-07

申请号：US14681505

申请日：2015-04-08

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/76877 ,  H01L29/66833 ,  H01L29/7926

摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

摘要翻译： 提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。 第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

公开(公告)号：US09183893B2

公开(公告)日：2015-11-10

申请号：US14037547

申请日：2013-09-26

申请人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

发明人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

IPC分类号： G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

公开(公告)号：US20140306279A1

公开(公告)日：2014-10-16

申请号：US14191542

申请日：2014-02-27

申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L23/00 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.

摘要翻译： 半导体存储器件包括：衬底，其包括单元区域和互连区域;相邻的从单元区域中的衬底垂直延伸的第一和第二排垂直沟道以及堆叠在衬底上的字线层。 每层包括第一行垂直通道通过的第一字线和第二行垂直通道通过的第二字线，并且字线包括延伸到互连区域中的相应字线焊盘。 隔离图案分离单元区域和互连区域中的第一和第二字线。 第一和第二多个接触插塞设置在互连区域中的隔离图案的相对侧上，并与字线焊盘接触。

公开(公告)号：US09875931B2

公开(公告)日：2018-01-23

申请号：US15201922

申请日：2016-07-05

申请人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US09299707B2

公开(公告)日：2016-03-29

申请号：US14150452

申请日：2014-01-08

申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C16/14

CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。