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    Semiconductor devices and methods of fabricating the same
    1.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08587052B2

    公开(公告)日：2013-11-19

    申请号：US13402171

    申请日：2012-02-22

    申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

    摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

    摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130032875A1

    公开(公告)日：2013-02-07

    申请号：US13402171

    申请日：2012-02-22

    申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    IPC分类号： H01L29/792 ,  H01L29/78

    CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

    摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

    摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。

    Three-dimensional semiconductor memory device
    4.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US09111617B2

    公开(公告)日：2015-08-18

    申请号：US13585963

    申请日：2012-08-15

    申请人： Sunil Shim ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

    发明人： Sunil Shim ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

    IPC分类号： H01L29/78 ,  G11C16/04 ,  H01L27/115

    CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

    摘要翻译： 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

    LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME
    6.
    发明申请
    LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME 有权
    闪存存储器件的本地自动提升方法和使用其的程序方法

    公开(公告)号：US20110103154A1

    公开(公告)日：2011-05-05

    申请号：US12917634

    申请日：2010-11-02

    申请人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

    发明人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

    IPC分类号： G11C16/12 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/3418

    摘要： Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.

    摘要翻译： 提供了一种闪存器件的局部自增强方法，其包括至少一个具有分别连接到字线的存储单元的串。 局部自增强方法包括在串的通道处形成势阱，并在势阱处形成位于所选存储单元的通道两侧的电势壁。 所选择的存储单元的通道在局部受到潜在的壁限制，并且当将程序电压施加到所选择的存储单元时升压。

    Three-dimensional semiconductor memory devices
    8.
    发明授权
    Three-dimensional semiconductor memory devices 有权
    三维半导体存储器件

    公开(公告)号：US08754466B2

    公开(公告)日：2014-06-17

    申请号：US13652998

    申请日：2012-10-16

    申请人： Janggn Yun ,  Kwang Soo Seol ,  Jungdal Choi

    发明人： Janggn Yun ,  Kwang Soo Seol ,  Jungdal Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7827 ,  H01L27/1157 ,  H01L27/11582

    摘要： Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.

    摘要翻译： 提供三维（3D）半导体存储器件。 根据3D半导体存储器件，栅极结构包括交替层叠在半导体衬底上的栅极图案和绝缘图案。 垂直有源图案穿过栅极结构。 栅介质层设置在垂直有源图案的侧壁和每个栅极图案之间。 半导体图案设置在栅极结构上并连接到垂直有源图案。 串联漏极区域形成在半导体图案的一部分中并且与垂直有源图案间隔开。