摘要:
A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.
摘要:
Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
摘要:
Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.
摘要:
According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.
摘要:
A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.
摘要:
A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.
摘要:
A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.
摘要:
Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.
摘要:
The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.
摘要:
A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure.At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.