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公开(公告)号：US07436694B2
公开(公告)日：2008-10-14
申请号：US11444295
申请日：2006-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。
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公开(公告)号：US20070047292A1
公开(公告)日：2007-03-01
申请号：US11444295
申请日：2006-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。
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公开(公告)号：US08400214B2
公开(公告)日：2013-03-19
申请号：US13188348
申请日：2011-07-21
申请人： Dieter Draxelmayr
发明人： Dieter Draxelmayr
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/3022 , H03F3/45991 , H03F2203/30024 , H03F2203/30061 , H03F2203/45138
摘要： This disclosure describes at least one class AB amplifier output stage circuit arrangement that can operate at low supply voltages, with minimum current generated. Furthermore, at least one class AB amplifier stage circuit arrangement described herein reacts favorably to a supply voltage, that is, exhibits a good power supply rejection ratio. Moreover, this disclosure describes class AB amplifier output stage circuit arrangements that include a negative channel metal oxide semiconductor (NMOS) transistor current mirror arrangement and a positive channel metal oxide semiconductor (PMOS) transistor current mirror arrangement. In some implementations, a monitoring circuit may be coupled to a class AB amplifier output stage circuit arrangement to offset mismatch that may occur in the class AB amplifier output stage.
摘要翻译： 本公开描述了至少一个类AB放大器输出级电路装置，其可以在产生最小电流的情况下以低电源电压工作。 此外，本文所述的至少一个AB类放大器级电路装置对电源电压有利地反应，即，表现出良好的电源抑制比。 此外，本公开描述了AB类放大器输出级电路布置，其包括负沟道金属氧化物半导体（NMOS）晶体管电流镜布置和正沟道金属氧化物半导体（PMOS）晶体管电流镜布置。 在一些实现中，监控电路可以耦合到AB类放大器输出级电路装置，以消除AB类放大器输出级中可能发生的失配。
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公开(公告)号：US20120081166A1
公开(公告)日：2012-04-05
申请号：US12894320
申请日：2010-09-30
申请人： Dieter Draxelmayr
发明人： Dieter Draxelmayr
IPC分类号： H03L5/00
CPC分类号： H03K3/356104 , H03K3/012
摘要： Some embodiments of the present disclosure relate to a level shifter that provides improved response time and/or low static power dissipation compared to conventional level shifters. In some embodiments, a level shifter circuit includes an input terminal coupled to a first semiconductor device, and an output terminal coupled to a second semiconductor device. The first semiconductor device is designed to operate over a first voltage range associated with an input signal, and the second semiconductor device is designed to operate over a second, different voltage range associated with an latched output signal. To transform the input voltage range to the output voltage range, the level shifter circuit includes a signal analyzer and an output latch, wherein the signal analyzer includes at least one state change element for setting a voltage level of the latched output signal.
摘要翻译： 本公开的一些实施例涉及与常规电平转换器相比提供改善的响应时间和/或低静态功耗的电平转换器。 在一些实施例中，电平移位器电路包括耦合到第一半导体器件的输入端子和耦合到第二半导体器件的输出端子。 第一半导体器件被设计为在与输入信号相关联的第一电压范围上工作，并且第二半导体器件被设计为在与锁存的输出信号相关联的第二不同电压范围上工作。 为了将输入电压范围转换为输出电压范围，电平移位器电路包括信号分析器和输出锁存器，其中信号分析器包括用于设置锁存输出信号的电压电平的至少一个状态改变元件。
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公开(公告)号：US08067958B2
公开(公告)日：2011-11-29
申请号：US12685894
申请日：2010-01-12
申请人： Dieter Draxelmayr
发明人： Dieter Draxelmayr
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03H11/30
摘要： Implementations to mitigating side effects of impedance transformation circuits are described. In particular, mitigation circuitry may be coupled to a high impedance circuit to minimize or eliminate non-linear output of the high impedance circuit in order to provide a well-defined bias voltage to the input of a buffer or amplifier device coupled to a capacitive sensor. Additionally, the mitigation circuitry may be coupled to the high impedance circuit to reduce or eliminate rectifying effects of the high impedance circuit. Accordingly, a bias voltage can be utilized to provide a stable operating point of the buffer or amplifier device via a high impedance circuit utilizing one or more impedance transformations.
摘要翻译： 描述了减轻阻抗变换电路的副作用的实现。 特别地，缓解电路可以耦合到高阻抗电路以最小化或消除高阻抗电路的非线性输出，以便向连接到电容传感器的缓冲器或放大器装置的输入提供良好限定的偏置电压 。 此外，缓解电路可以耦合到高阻抗电路以减少或消除高阻抗电路的整流效应。 因此，可以利用偏置电压来通过利用一个或多个阻抗变换的高阻抗电路来提供缓冲器或放大器装置的稳定工作点。
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公开(公告)号：US07911275B2
公开(公告)日：2011-03-22
申请号：US12418634
申请日：2009-04-06
申请人： Dieter Draxelmayr
发明人： Dieter Draxelmayr
IPC分类号： H03F3/45
CPC分类号： H03G1/0029 , H03F3/45183 , H03F2200/408 , H03F2203/45244 , H03F2203/45508 , H03F2203/45652
摘要： This disclosure relates to maintaining constant gain within multi-stage amplifiers.
摘要翻译： 本公开涉及在多级放大器内保持恒定的增益。
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公开(公告)号：US07804343B2
公开(公告)日：2010-09-28
申请号：US12055375
申请日：2008-03-26
申请人： Dieter Draxelmayr
发明人： Dieter Draxelmayr
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/0896 , H03L7/093
摘要： One embodiment described is a charge pump arrangement that includes a regulator to regulate signals associated with two output nodes. A switching mechanism may be coupled to the regulator. The switching mechanism is to interrupt the regulator.
摘要翻译： 所描述的一个实施例是电荷泵装置，其包括用于调节与两个输出节点相关联的信号的调节器。 开关机构可以耦合到调节器。 切换机制是中断调节器。
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公开(公告)号：US07750687B2
公开(公告)日：2010-07-06
申请号：US11546009
申请日：2006-10-11
IPC分类号： H03K3/00
CPC分类号： H03K19/018521
摘要： A circuit arrangement includes a first level shifter, an output stage, and a feedback circuit. The first level shifter is coupled to receive an input signal having a first voltage level from an input terminal, and is configured to provide a level-shifted signal having a second voltage level higher than the first voltage level. The output stage includes a first transistor that has a control terminal operably coupled to an output of the first level shifter. The output stage is configured to provide at an output terminal of the output stage an output signal based on the level-shifted signal. The feedback circuit is configured to feed back the output signal to the output of the first level shifter.
摘要翻译： 电路装置包括第一电平移位器，输出级和反馈电路。 第一电平移位器被耦合以从输入端子接收具有第一电压电平的输入信号，并且被配置为提供具有高于第一电压电平的第二电压电平的电平移位信号。 输出级包括具有可操作地耦合到第一电平移位器的输出的控制端的第一晶体管。 输出级被配置为在输出级的输出端提供基于电平移位信号的输出信号。 反馈电路被配置为将输出信号反馈到第一电平移位器的输出。
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公开(公告)号：US07663353B2
公开(公告)日：2010-02-16
申请号：US11586417
申请日：2006-10-25
申请人： Dieter Draxelmayr
发明人： Dieter Draxelmayr
IPC分类号： G05F1/44
CPC分类号： G05F1/575
摘要： A circuit arrangement for voltage regulation comprises an output, a controllable output transistor connected to the output, an error detection circuit, and a monitoring control circuit. A voltage-regulated output potential can be tapped off the output, the controllable output transistor is connected to the output on a load side and the output transistor comprises a control terminal. The error detection circuit provides a regulating signal if a deviation between the output potential or a potential derived from the output potential and a desired value occurs. By means of the regulating signal the control terminal can be charged or discharged dependent on the deviation and the monitoring control circuit monitors the regulating signal and performs, if the regulating signal lies outside a predetermined range, an additional charging or discharging of the control terminal until the regulating signal lies within the predetermined range.
摘要翻译： 用于电压调节的电路装置包括输出，连接到输出的可控输出晶体管，误差检测电路和监视控制电路。 电压调节输出电位可从输出端分出，可控输出晶体管连接到负载侧的输出，输出晶体管包括控制端。 如果出现输出电位或从输出电位导出的电位与期望值之间的偏差，则误差检测电路提供调节信号。 通过调节信号，控制端子可以根据偏差进行充电或放电，并且监视控制电路监视调节信号，并且如果调节信号位于预定范围之外，则执行控制终端的附加充电或放电直到 调节信号处于预定范围内。
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公开(公告)号：US20080094099A1
公开(公告)日：2008-04-24
申请号：US11543009
申请日：2006-10-04
申请人： Ban Hok Goh , Dieter Draxelmayr
发明人： Ban Hok Goh , Dieter Draxelmayr
IPC分类号： H03K19/003
CPC分类号： H03K5/13 , H03K2005/00032 , H03K2005/00045 , H03K2005/00136 , H03L7/0812 , H04L25/0272
摘要： A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.
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