公开(公告)号：US06737671B2

公开(公告)日：2004-05-18

申请号：US10180254

申请日：2002-06-26

申请人： Joerg Vollrath ,  Philip Moore ,  Ulrich Zimmermann

发明人： Joerg Vollrath ,  Philip Moore ,  Ulrich Zimmermann

IPC分类号： H01L2358

CPC分类号： G01R31/3008

摘要： A current measurement circuit and method for testing a semiconductor device is provided. The method includes the steps of providing a semiconductor integrated circuit device including a voltage regulating circuit, the voltage regulating circuit being activated as needed to maintain a required voltage level; monitoring the voltage regulating circuit to determine a number of times it is activated during a sample period; and comparing the number of activations to a predetermined limit whereby if the number of activations exceeds the predetermined limit the semiconductor device is defective. The current measurement circuit includes an external clock for providing a clock signal; a first counter for counting when the voltage regulating circuit is activated; a second counter for counting clock cycles of a sample period; and a register for storing the number of activations, wherein the number of activations represents a relative current consumption value of the semiconductor device.

公开(公告)号：US06981175B2

公开(公告)日：2005-12-27

申请号：US09967008

申请日：2001-09-28

申请人： Joerg Vollrath ,  Philip Moore

发明人： Joerg Vollrath ,  Philip Moore

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F12/02 ,  G11C29/00 ,  G11C29/02 ,  G11C29/42 ,  H04L1/22

CPC分类号： G06F11/1004 ,  G11C29/02 ,  G11C29/027 ,  G11C29/42 ,  G11C29/785

摘要： A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement address identifying one of the storage elements of the memory array to be replaced by an associated one of the replacement storage elements and forming a respective 2m bit row or 2n bit column of a fuse array; a vector generator operable to produce a 2n bit row vector based on the rows of the fuse array and to produce a 2m bit column vector based on the columns of the fuse array; and a compression unit operable to produce a row checksum from the row vector and to produce a column checksum from the column vector.

摘要翻译： 存储器包括：具有多个存储元件的存储器阵列; 多个替换存储元件; 多个地址熔丝单元，每个地址熔丝单元具有多个可熔链，并且可操作以存储替换地址，每个替换地址标识存储器阵列的存储元件之一，以被相关联的一个替换存储元件代替并形成 保险丝阵列的相应的2 比特列或2 比特列; 矢量发生器，其可操作以基于所述保险丝阵列的行产生2位比特行向量，并且基于所述保险丝的列产生2比特列向量 阵列 以及压缩单元，其可操作以从所述行向量产生行校验和，并从所述列向量产生列校验和。

公开(公告)号：US06304479B1

公开(公告)日：2001-10-16

申请号：US09602758

申请日：2000-06-23

申请人： Joerg Vollrath ,  Michael Fera ,  Philip Moore

发明人： Joerg Vollrath ,  Michael Fera ,  Philip Moore

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C7/18

摘要： A memory array, in accordance with the invention, includes a plurality of memory cells disposed in an array. A plurality of bitlines are included for reading and writing data to and from the memory cells. The plurality of bitlines include a first group of bitlines and a second group of bitlines. Each bitline of the first group is interposed between bitlines of the second group, and each bitline of the second group is interposed between bitlines of the first group. The first group of bitlines are active when the second group of bitlines are inactive, and the second group of bitlines are active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.

摘要翻译： 根据本发明的存储器阵列包括以阵列布置的多个存储单元。 包括用于从存储器单元读取和写入数据的多个位线。 多个位线包括第一组位线和第二组位线。 第一组的每个位线插在第二组的位线之间，并且第二组的每个位线插在第一组的位线之间。 当第二组位线不活动时，第一组位线是活动的，并且当第一组位线不活动时第二组位线是活动的，使得相邻的非活动位线提供屏蔽以防止有源位线之间的交叉耦合。

公开(公告)号：US07402859B2

公开(公告)日：2008-07-22

申请号：US11079884

申请日：2005-03-15

申请人： Joerg Vollrath ,  Marcin Gnat ,  Ralf Schneider ,  Stephan Schroeder

发明人： Joerg Vollrath ,  Marcin Gnat ,  Ralf Schneider ,  Stephan Schroeder

IPC分类号： H01L27/108 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78618

摘要： A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

摘要翻译： 场效应半导体包括在半导体层的表面上彼此相邻布置的半导体层中具有表面的第一和第二半导体区域的半导体层，在第一半导体区域和第二半导体区域之间的绝缘层 半导体区域，半导体层的表面上的半导体条，该半导体条与第一半导体区域和第二半导体区域重叠，并与其邻接。 至少在绝缘层的区域中，栅极与半导体条重叠。 栅介质将栅极与半导体条绝缘在第一半导体区和第二半导体区之间。 半导体条和栅极形成为使得半导体条以第一预定栅极电压电绝缘并且在第二预定栅极电压下导电。

公开(公告)号：US20080151594A1

公开(公告)日：2008-06-26

申请号：US11958639

申请日：2007-12-18

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C17/16 ,  G11C17/165 ,  G11C29/006 ,  G11C29/56 ,  G11C2207/2254

摘要： A semiconductor device with a plurality of one time programmable elements and to a method for programming a semiconductor device, and to a method for operating a semiconductor device is disclosed. One embodiment provides a method for programming a semiconductor device comprising a plurality of one time programmable elements that form a group of one time programmable elements. The one time programmable elements of the group are left in a non-programmed state if a first information is to be stored by the group. A first one time programmable element of the group is programmed if a second information differing from the first information is to be stored by the group.

摘要翻译： 公开了一种具有多个一次可编程元件的半导体器件和用于编程半导体器件的方法以及用于操作半导体器件的方法。 一个实施例提供了一种用于编程半导体器件的方法，该半导体器件包括形成一组一次可编程元件的多个一次可编程元件。 如果要由组存储第一信息，则该组的一次可编程元件保持在非编程状态。 如果组中存储与第一信息不同的第二信息，则对该组的第一个一次可编程元件进行编程。

公开(公告)号：US07196537B2

公开(公告)日：2007-03-27

申请号：US11092963

申请日：2005-03-30

申请人： Aurel von Campenhausen ,  Joerg Vollrath ,  Ralf Schneider ,  Marcin Gnat

发明人： Aurel von Campenhausen ,  Joerg Vollrath ,  Ralf Schneider ,  Marcin Gnat

IPC分类号： G01R31/26

CPC分类号： G11C29/1201 ,  G01R31/275 ,  G01R31/2884 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/5002

摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.

摘要翻译： 集成电路包括电路部件，第一控制电路和可切换电阻网络。 输入电压被馈送到输入侧的电路部件。 由第一控制电路产生的控制信号被馈送到电路部件的控制端。 利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。 集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。 集成电路的晶体管的特性曲线族由集成电路确定。

公开(公告)号：US07051253B2

公开(公告)日：2006-05-23

申请号：US09931125

申请日：2001-08-16

申请人： Randall Rooney ,  Joerg Vollrath

发明人： Randall Rooney ,  Joerg Vollrath

IPC分类号： G11C29/00

CPC分类号： G11C29/10

摘要： According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.

公开(公告)号：US20070211509A1

公开(公告)日：2007-09-13

申请号：US11715839

申请日：2007-03-08

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconductor memory has memory cells, with at least one pair of bit lines which comprises a first bit line and a second bit line, and with at least one sense amplifier which has the first bit line and the second bit line connected to it. The bit lines respectively have a first conductor track structure and a second conductor track structure, where the memory cells are respectively connected to the second conductor track structure, and where the first conductor track structure is respectively interposed between the sense amplifier and the second conductor track structure of the respective bit line and is arranged at a greater distance from the substrate area than the respective second conductor track structure.

摘要翻译： 集成半导体存储器具有存储单元，其中至少一对位线包括第一位线和第二位线，以及至少一个读出放大器，其具有与其连接的第一位线和第二位线。 位线分别具有第一导体轨道结构和第二导体轨道结构，其中存储单元分别连接到第二导体轨道结构，并且其中第一导体轨道结构分别插入在读出放大器和第二导体轨道之间 相对于位线的结构，并且布置在距离基板区域比相应的第二导体轨道结构更远的距离处。

公开(公告)号：US07203883B2

公开(公告)日：2007-04-10

申请号：US11086655

申请日：2005-03-23

申请人： Aurel von Campenhausen ,  Marcin Gnat ,  Joerg Vollrath ,  Ralf Schneider

发明人： Aurel von Campenhausen ,  Marcin Gnat ,  Joerg Vollrath ,  Ralf Schneider

IPC分类号： G06F11/00

CPC分类号： G11C29/50012 ,  G01R31/3016 ,  G11C29/02

摘要： An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

摘要翻译： 可以在正常运行状态和测试运行状态下运行的集成半导体存储器包括具有用于施加输入信号的输入端的电流脉冲电路。 电流脉冲电路经由用于承载电流的互连件连接到输出端子。 在测试操作状态下，当前脉冲电路在第一测试周期中产生具有第一预定持续时间的至少一个第一电流脉冲，以及在随后的第二测试周期中具有第二未知持续时间的至少一个第二电流脉冲。 除了在正常操作状态下在互连上流动的第一电流之外，第二电流在第一测试周期期间在互连上流动，并且第三电流在测试操作状态期间在第二测试周期期间流动。

公开(公告)号：US20060198223A1

公开(公告)日：2006-09-07

申请号：US11364365

申请日：2006-03-01

申请人： Joerg Vollrath ,  Marcin Gnat

发明人： Joerg Vollrath ,  Marcin Gnat

IPC分类号： G11C7/02

CPC分类号： G11C29/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097 ,  G11C29/025 ,  G11C2029/1204

摘要： An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to “post-sense coupling” effects upon activation of the sense amplifiers in conjunction with capacitive coupling effects between bit lines, potential changes occur on adjacent bit lines. The integrated semiconductor memory makes it possible to simulate parasitic coupling effects between adjacent bit lines in a functional test in which the first and second sense amplifiers can be activated in temporarily delayed fashion. As a result, the test severity can be improved and test time can be saved.

摘要翻译： 集成半导体存储器包括存储单元阵列，其中第一读出放大器布置在存储单元阵列的右手侧，第二读出放大器布置在存储单元阵列的左侧。 由于感测放大器的激活与位线之间的电容耦合效应的“后感测耦合”效应，在相邻位线上发生电位变化。 集成半导体存储器使得可以在功能测试中模拟相邻位线之间的寄生耦合效应，其中第一和第二读出放大器可以以暂时延迟的方式被激活。 因此，可以提高测试严重性，并可以节省测试时间。