公开(公告)号：US20110104913A1

公开(公告)日：2011-05-05

申请号：US12590090

申请日：2009-11-02

Applicant: Jonathan R. Hinkle

Inventor： Jonathan R. Hinkle

IPC: H01R12/00

CPC classification number: H01R43/205 ,  H01R12/57 ,  H01R12/721

Abstract: An edge card connector includes: a substantially rigid, insulating housing having internal electrical contacts to engage the edge of a first circuit board inserted into the housing; solder balls arranged on an outer surface of the housing in a selected pattern to establish connections to corresponding conductive pads on a second circuit board when the solder balls are at least partially melted; and, electrical connections between the internal electrical contacts and the solder balls. The socket may contain additional features for added strength, ease of assembly, and other purposes. The system is assembled by placing the socket onto a circuit board, aligning the solder balls with respective contact pads, and fusing the solder balls to establish electrical connectivity. A standoff structure may be provided to avoid excessive compaction of the solder balls.

Abstract translation: 边缘卡连接器包括：基本上刚性的绝缘壳体，其具有内部电触头以接合插入到壳体中的第一电路板的边缘; 焊球以选定的图案布置在外壳的外表面上，以在焊球至少部分熔化时建立与第二电路板上的对应导电焊盘的连接; 以及内部电触头和焊球之间的电连接。 插座可能包含额外的功能，增加强度，易于组装和其他目的。 通过将插座放置在电路板上，将焊球对准相应的接触垫并将焊球熔合以建立电连接来组装该系统。 可以提供间隔结构以避免焊球的过度压实。

公开(公告)号：US20080301352A1

公开(公告)日：2008-12-04

申请号：US11757942

申请日：2007-06-04

Applicant: P. Maurice Bland ,  Moises Cases ,  Jonathan R. Hinkle ,  Pravin Patel ,  Nam H. Pham

Inventor： P. Maurice Bland ,  Moises Cases ,  Jonathan R. Hinkle ,  Pravin Patel ,  Nam H. Pham

IPC: G06F13/40

CPC classification number: G06F13/4086

Abstract: A system and method for implementing a bus. In one embodiment, the system includes a bus switch operative to couple to a bus, and a plurality of trace segments coupled to the bus switch, where the trace segments have different lengths. The bus switch is operative to connect one of the trace segments to the bus based on at least one system requirement, and the selected trace segment cancels signal reflections on the bus.

Abstract translation: 一种用于实现总线的系统和方法。 在一个实施例中，系统包括可操作以耦合到总线的总线开关和耦合到总线开关的多个迹线段，其中迹线段具有不同的长度。 总线开关可以根据至少一个系统要求将一个跟踪段连接到总线，并且所选择的跟踪段取消总线上的信号反射。

公开(公告)号：US08583869B2

公开(公告)日：2013-11-12

申请号：US13082312

申请日：2011-04-07

Applicant: Jonathan R. Hinkle ,  Paul Sweere

Inventor： Jonathan R. Hinkle ,  Paul Sweere

IPC: G06F12/00

CPC classification number: G06F13/20 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/205 ,  G11C5/04

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract translation: 提供了一个存储器/存储模块，它实现与双数据速率兼容插座上的串行高级技术附件（SATA）或串行连接SCSI（SAS）信号兼容的固态驱动器。 可拆卸子卡可以耦合到存储器模块，用于将存储器总线电压转换为存储器模块上的存储器件的第二电压。 此外，提供了主机系统上的混合存储器总线，其支持DDR兼容存储器模块和/或SATA / SAS兼容存储器模块。 在一个示例中，存储器/存储模块耦合到第一总线（DDR3兼容插座）以获得电压和/或其他信号，但是使用第二总线进行数据传输。 在另一示例中，存储器模块可以重新调整/重新使用通常携带非数据信号的电路径，以用于/从存储/存储模块的数据业务。 用于存储/存储模块的这种数据业务允许同一存储器总线上的其他存储器模块的并发数据通信。

公开(公告)号：US20110153903A1

公开(公告)日：2011-06-23

申请号：US12975347

申请日：2010-12-21

Applicant: Jonathan R. Hinkle ,  Paul Sweere

Inventor： Jonathan R. Hinkle ,  Paul Sweere

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/205 ,  G11C5/04

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract translation: 提供了一个存储器/存储模块，它实现与双数据速率兼容插座上的串行高级技术附件（SATA）或串行连接SCSI（SAS）信号兼容的固态驱动器。 可拆卸子卡可以耦合到存储器模块，用于将存储器总线电压转换为存储器模块上的存储器件的第二电压。 此外，提供了主机系统上的混合存储器总线，其支持DDR兼容存储器模块和/或SATA / SAS兼容存储器模块。 在一个示例中，存储器/存储模块耦合到第一总线（DDR3兼容插座）以获得电压和/或其他信号，但是使用第二总线进行数据传输。 在另一示例中，存储器模块可以重新调整/重新使用通常携带非数据信号的电路径，以用于/从存储/存储模块的数据业务。 用于存储/存储模块的这种数据业务允许同一存储器总线上的其他存储器模块的并发数据通信。

公开(公告)号：US20100008175A1

公开(公告)日：2010-01-14

申请号：US12500471

申请日：2009-07-09

Applicant: Paul Sweere ,  Jonathan R. Hinkle

Inventor： Paul Sweere ,  Jonathan R. Hinkle

IPC: G11C5/14

CPC classification number: G11C5/141 ,  G06F11/1441 ,  G06F12/0866 ,  G11C5/14 ,  G11C5/143 ,  G11C11/005 ,  Y02D10/13

Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.

Abstract translation: 提供了一种存储器模块，其包括具有与主机系统，易失性存储器，非易失性存储器和逻辑器件的接口的衬底。 逻辑设备可以接收外部触发事件的指示符，并且在接收到这样的指示器时将数据从易失性存储器设备复制到非易失性存储器设备。 当触发事件的指示符已经清除时，逻辑器件将数据从非易失性恢复到易失性存储器件。 存储器模块可以包括被外部电源充电的无源备用电源（例如超级电容器），并且暂时向存储器模块提供电力以将数据从易失性存储器复制到非易失性存储器。 存储器模块内的电压检测器可以监视外部电源的电压，并且如果外部电源的电压低于阈值电平，则产生功率损失事件的指示器。

公开(公告)号：US20100008034A1

公开(公告)日：2010-01-14

申请号：US12172580

申请日：2008-07-14

Applicant: Jonathan R. Hinkle

Inventor： Jonathan R. Hinkle

IPC: G06F1/16 ,  H01S4/00

CPC classification number: G06F1/20 ,  H05K1/117 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/047 ,  H05K2201/056 ,  H05K2201/09745 ,  H05K2201/10159 ,  H05K2203/302 ,  Y10T29/49002

Abstract: Memory systems and methods of forming memory modules. In one embodiment, a computer memory system includes a substantially tubular frame with an elongate card edge extending along the frame. A flexible circuit comprising a flexible substrate, a plurality of memory chips affixed to the flexible substrate, and a plurality of electrical terminals interconnected with the memory chips, is secured along a perimeter of the tubular frame with the electrical terminals arranged along the card edge.

Abstract translation: 内存系统和形成内存模块的方法。 在一个实施例中，计算机存储器系统包括具有沿框架延伸的细长卡边缘的基本上管状的框架。 包括柔性基板，固定到柔性基板的多个存储芯片以及与存储芯片互连的多个电端子的柔性电路沿着管状框架的周边被固定，电端子沿卡边缘布置。

公开(公告)号：US20090164672A1

公开(公告)日：2009-06-25

申请号：US11960884

申请日：2007-12-20

Applicant: Justin P. Bandholz ,  Jonathan R. Hinkle ,  Devarshi S. Patel ,  Pravin S. Patel ,  Kevin M. Reinberg

Inventor： Justin P. Bandholz ,  Jonathan R. Hinkle ,  Devarshi S. Patel ,  Pravin S. Patel ,  Kevin M. Reinberg

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Computer memory subsystems are disclosed for enhancing signal quality that include: one or more memory modules; a memory bus; and a memory controller connected to the memory modules through the memory bus, the memory controller including a reception buffer connected to the memory bus, the reception buffer capable of receiving an input signal from one of the memory modules, the memory controller including a reception characteristics table capable of storing reception characteristics for each of the memory modules connected to the memory controller, the memory controller including an equalizer connected to the reception buffer and the reception characteristics table, the equalizer capable of equalizing the received input signal in dependence upon the reception characteristics for the memory module from which the input signal was received, and the memory controller including memory controller logic connected to the equalizer, the memory controller logic capable of processing the equalized input signal.

Abstract translation: 公开了用于增强信号质量的计算机存储器子系统，其包括：一个或多个存储器模块; 内存总线 以及通过存储器总线连接到存储器模块的存储器控​​制器，所述存储器控制器包括连接到存储器总线的接收缓冲器，所述接收缓冲器能够接收来自所述存储器模块之一的输入信号，所述存储器控制器包括接收特性 表能够存储连接到存储器控制器的每个存储器模块的接收特性，存储器控制器包括连接到接收缓冲器的均衡器和接收特性表，该均衡器能够根据接收特性来均衡接收到的输入信号 对于从其接收输入信号的存储器模块，存储器控制器包括连接到均衡器的存储器控​​制器逻辑，该存储器控制器逻辑能够处理均衡的输入信号。

公开(公告)号：US08799606B2

公开(公告)日：2014-08-05

申请号：US11960884

申请日：2007-12-20

Applicant: Justin P. Bandholz ,  Jonathan R. Hinkle ,  Devarshi S. Patel ,  Pravin S. Patel ,  Kevin M. Reinberg

Inventor： Justin P. Bandholz ,  Jonathan R. Hinkle ,  Devarshi S. Patel ,  Pravin S. Patel ,  Kevin M. Reinberg

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: Computer memory subsystems are disclosed for enhancing signal quality that include: one or more memory modules; a memory bus; and a memory controller connected to the memory modules through the memory bus, the memory controller including a reception buffer connected to the memory bus, the reception buffer capable of receiving an input signal from one of the memory modules, the memory controller including a reception characteristics table capable of storing reception characteristics for each of the memory modules connected to the memory controller, the memory controller including an equalizer connected to the reception buffer and the reception characteristics table, the equalizer capable of equalizing the received input signal in dependence upon the reception characteristics for the memory module from which the input signal was received, and the memory controller including memory controller logic connected to the equalizer, the memory controller logic capable of processing the equalized input signal.

Abstract translation: 公开了用于增强信号质量的计算机存储器子系统，其包括：一个或多个存储器模块; 内存总线 以及通过存储器总线连接到存储器模块的存储器控​​制器，所述存储器控制器包括连接到存储器总线的接收缓冲器，所述接收缓冲器能够接收来自所述存储器模块之一的输入信号，所述存储器控制器包括接收特性 表能够存储连接到存储器控制器的每个存储器模块的接收特性，存储器控制器包括连接到接收缓冲器的均衡器和接收特性表，该均衡器能够根据接收特性来均衡接收到的输入信号 对于从其接收输入信号的存储器模块，存储器控制器包括连接到均衡器的存储器控​​制器逻辑，该存储器控制器逻辑能够处理均衡的输入信号。

公开(公告)号：US08325554B2

公开(公告)日：2012-12-04

申请号：US12500471

申请日：2009-07-09

Applicant: Paul Sweere ,  Jonathan R. Hinkle

Inventor： Paul Sweere ,  Jonathan R. Hinkle

IPC: G11C5/14

CPC classification number: G11C5/141 ,  G06F11/1441 ,  G06F12/0866 ,  G11C5/14 ,  G11C5/143 ,  G11C11/005 ,  Y02D10/13

Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.

Abstract translation: 提供了一种存储器模块，其包括具有与主机系统，易失性存储器，非易失性存储器和逻辑器件的接口的衬底。 逻辑设备可以接收外部触发事件的指示符，并且在接收到这样的指示器时将数据从易失性存储器设备复制到非易失性存储器设备。 当触发事件的指示符已经清除时，逻辑器件将数据从非易失性恢复到易失性存储器件。 存储器模块可以包括被外部电源充电的无源备用电源（例如超级电容器），并且暂时向存储器模块提供电力以将数据从易失性存储器复制到非易失性存储器。 存储器模块内的电压检测器可以监视外部电源的电压，并且如果外部电源的电压低于阈值电平，则产生功率损失事件的指示器。

公开(公告)号：US08107254B2

公开(公告)日：2012-01-31

申请号：US12274407

申请日：2008-11-20

Applicant: Justin P. Bandholz ,  Jonathan R. Hinkle ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Jonathan R. Hinkle ,  Pravin Patel

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H05K1/0239 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09809

Abstract: A printed circuit board (‘PCB’) with a capacitor integrated within a via of the PCB, the PCB including layers of laminate; a via that includes a via hole traversing layers of the PCB, the via hole characterized by a generally tubular inner surface; a capacitor integrated within the via, the capacitor including two capacitor plates, an inner plate and an outer plate, the two plates composed of electrically conductive material disposed upon the inner surface of the via hole, both plates traversing layers of the laminate, the inner plate traversing more layers of the laminate than are traversed by the outer plate; and a layer of dielectric material disposed between the two plates.

Abstract translation: 印刷电路板（“PCB”），其电容器集成在PCB的通孔内，PCB包括层压板; 通孔，其包括穿过所述PCB的层的通孔，所述通孔的特征在于大致管状的内表面; 集成在通孔内的电容器，电容器包括两个电容器板，内板和外板，两个板由设置在通孔内表面上的导电材料组成，两个板横跨层压板，内部 板穿过层压板比由外板穿过的多层; 以及设置在两个板之间的介电材料层。