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    Duty cycle corrector
    1.
    发明申请
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US20060214714A1

    公开(公告)日：2006-09-28

    申请号：US11442842

    申请日：2006-05-30

    申请人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    发明人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    IPC分类号： H03K3/017

    CPC分类号： G06F1/04 ,  H03K5/1565

    摘要： A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.

    摘要翻译： 公开了包括第一，第二电路和第三电路的占空比校正器。 第三电路被配置为响应于由第一电路和第二电路调节的电荷流量获得阈值，其中第一电路被配置为接收时钟信号并且在时钟的第一转变处改变电荷流 信号。 第二电路被配置为在时钟信号的第二转变处改变电荷流。 第一电路和第二电路被配置为响应于获得阈值来改变电荷流。

    Duty cycle corrector
    2.
    发明申请
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US20060152265A1

    公开(公告)日：2006-07-13

    申请号：US11032459

    申请日：2005-01-10

    申请人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    发明人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    IPC分类号： H03K3/017

    CPC分类号： G06F1/04 ,  H03K5/1565

    摘要： A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.

    摘要翻译： 一种占空比校正器，包括第一电路和第二电路。 第一电路被配置为接收具有第一相位和第二相位的时钟信号，并且基于第一相位的长度和第二相位的一部分来获得第一阈值，并且提供第一脉冲和对第一阈值的响应 值。 第二电路被配置为接收时钟信号并且基于第二相位的长度和第一相的一部分获得第二阈值，并且响应于第二阈值提供第二脉冲。 第一脉冲的开始和第二脉冲的开始之间的时间基本上是一个半个时钟周期。

    Duty cycle corrector
    3.
    发明授权
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US07230465B2

    公开(公告)日：2007-06-12

    申请号：US11032459

    申请日：2005-01-10

    申请人： Joonho Kim ,  Jung Pill Kim ,  Jonghee Han

    发明人： Joonho Kim ,  Jung Pill Kim ,  Jonghee Han

    IPC分类号： H03K3/017

    CPC分类号： G06F1/04 ,  H03K5/1565

    摘要： A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.

    摘要翻译： 一种占空比校正器，包括第一电路和第二电路。 第一电路被配置为接收具有第一相位和第二相位的时钟信号，并且基于第一相位的长度和第二相位的一部分来获得第一阈值，并且提供第一脉冲和对第一阈值的响应 值。 第二电路被配置为接收时钟信号并且基于第二相位的长度和第一相的一部分获得第二阈值，并且响应于第二阈值提供第二脉冲。 第一脉冲的开始和第二脉冲的开始之间的时间基本上是一个半个时钟周期。

    Duty cycle corrector
    4.
    发明授权
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US07304517B2

    公开(公告)日：2007-12-04

    申请号：US11442842

    申请日：2006-05-30

    申请人： Joonho Kim ,  Jung Pill Kim ,  Jonghee Han

    发明人： Joonho Kim ,  Jung Pill Kim ,  Jonghee Han

    IPC分类号： H03K3/017

    CPC分类号： G06F1/04 ,  H03K5/1565

    摘要： A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.

    摘要翻译： 公开了包括第一，第二电路和第三电路的占空比校正器。 第三电路被配置为响应于由第一电路和第二电路调节的电荷流量获得阈值，其中第一电路被配置为接收时钟信号并且在时钟的第一转变处改变电荷流 信号。 第二电路被配置为在时钟信号的第二转变处改变电荷流。 第一电路和第二电路被配置为响应于获得阈值来改变电荷流。

    DELAY LOCKED LOOP PHASE BLENDER CIRCUIT
    5.
    发明申请
    DELAY LOCKED LOOP PHASE BLENDER CIRCUIT 审中-公开
    延迟锁定环路相机电路

    公开(公告)号：US20050093594A1

    公开(公告)日：2005-05-05

    申请号：US10696920

    申请日：2003-10-30

    申请人： Jung Kim ,  Jonghee Han

    发明人： Jung Kim ,  Jonghee Han

    IPC分类号： H03K5/00 ,  H03K5/13 ,  H03L7/06 ,  H03L7/081

    CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071 ,  H03L7/0818

    摘要： Techniques and circuit configurations for fine phase adjustments, for example, in a delay-locked loop (DLL) circuit are provided. Multiple phase signals may be generated from a single current source by selectively coupling one or more delay elements to an output node of the current source. The delay elements may vary the timing of a signal generated by switching the current source.

    摘要翻译： 提供了用于精细相位调整的技术和电路配置，例如在延迟锁定环（DLL）电路中。 可以通过选择性地将一个或多个延迟元件耦合到电流源的输出节点，从单个电流源产生多个相位信号。 延迟元件可以改变通过切换电流源产生的信号的定时。

    Random access memory having self-adjusting off-chip driver
    6.
    发明申请
    Random access memory having self-adjusting off-chip driver 审中-公开
    具有自调节片外驱动器的随机存取存储器

    公开(公告)号：US20050083766A1

    公开(公告)日：2005-04-21

    申请号：US10690358

    申请日：2003-10-21

    申请人： Jung Kim ,  Jonghee Han

    发明人： Jung Kim ,  Jonghee Han

    IPC分类号： G11C7/10 ,  G11C11/4096 ,  H03K19/003 ,  G11C11/24

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4096 ,  H03K19/00384

    摘要： One embodiment of the present invention provides a random access memory device including a memory array, a level detector, and an off-chip driver circuit. The level detector monitors a source voltage and provides a level signal representative of a voltage range of the source voltage. The off-chip driver circuit is associated with the memory array and provides an output signal having at least one operating parameter, and adjusts the at least one operating parameter by adjusting a magnitude of at least one impedance based on the level signal.

    摘要翻译： 本发明的一个实施例提供一种包括存储器阵列，电平检测器和片外驱动电路的随机存取存储器件。 电平检测器监视源电压并提供表示源电压的电压范围的电平信号。 片外驱动器电路与存储器阵列相关联并提供具有至少一个操作参数的输出信号，并且通过基于电平信号调整至少一个阻抗的幅度来调整至少一个操作参数。

    Input buffer circuit including reference voltage monitoring circuit
    7.
    发明申请
    Input buffer circuit including reference voltage monitoring circuit 失效
    输入缓冲电路，包括参考电压监控电路

    公开(公告)号：US20050134331A1

    公开(公告)日：2005-06-23

    申请号：US10739097

    申请日：2003-12-19

    申请人： Jung Kim ,  Jonghee Han

    发明人： Jung Kim ,  Jonghee Han

    IPC分类号： H03B1/00 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/00384 ,  H03K19/018528

    摘要： A buffer circuit includes a differential amplifier, a buffering inverter, and a reference voltage monitoring circuit. The differential amplifier has a reference voltage and a current source as inputs. The buffering inverter has an output of the differential amplifier as an input. The reference voltage monitoring circuit includes two transistors and a second current source. An output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times. The buffer circuit can further include a driver circuit with a comparator. A method of managing signal propagation delays includes providing a differential amplifier, providing at least one buffering inverter, and providing a reference voltage monitoring circuit. The reference voltage monitoring circuit can maintain signal propagation delays as a reference voltage varies.

    摘要翻译： 缓冲电路包括差分放大器，缓冲反相器和参考电压监视电路。 差分放大器具有参考电压和电流源作为输入。 缓冲反相器具有差分放大器的输出作为输入。 参考电压监视电路包括两个晶体管和一个第二电流源。 参考电压监视电路的输出端连接到缓冲反相器，以便最小化参考电压值对信号传播延迟时间的影响。 缓冲电路还可以包括具有比较器的驱动电路。 管理信号传播延迟的方法包括提供差分放大器，提供至少一个缓冲反相器，以及提供参考电压监视电路。 参考电压监视电路可以在参考电压变化时保持信号传播延迟。