公开(公告)号：US12034459B2

公开(公告)日：2024-07-09

申请号：US18312834

申请日：2023-05-05

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Osamu Torii ,  Hiroshi Yao ,  Kiyotaka Iwasaki

IPC: H03M13/35 ,  G06F3/06 ,  G06F11/10 ,  G11B20/18 ,  G11C29/52 ,  H03M13/29 ,  G11C7/10 ,  G11C29/04

CPC classification number: H03M13/35 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957 ,  G11B20/1833 ,  G11C7/1006 ,  G11C2029/0411

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

公开(公告)号：US12265706B2

公开(公告)日：2025-04-01

申请号：US18396352

申请日：2023-12-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Yao ,  Shinichi Kanno ,  Kazuhiro Fukutomi

IPC: G06F3/06 ,  G06F12/02

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

公开(公告)号：US11893238B2

公开(公告)日：2024-02-06

申请号：US18155282

申请日：2023-01-17

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Yao ,  Shinichi Kanno ,  Kazuhiro Fukutomi

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0634 ,  G06F3/0641 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

公开(公告)号：US11683053B2

公开(公告)日：2023-06-20

申请号：US17178604

申请日：2021-02-18

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Osamu Torii ,  Hiroshi Yao ,  Kiyotaka Iwasaki

IPC: H03M13/00 ,  H03M13/35 ,  G06F11/10 ,  H03M13/29 ,  G06F3/06 ,  G11C29/52 ,  G11C7/10 ,  G11B20/18 ,  G11C29/04

CPC classification number: H03M13/35 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957 ,  G11B20/1833 ,  G11C7/1006 ,  G11C2029/0411

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.