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    Learning device
    2.
    发明授权
    Learning device 有权

    公开(公告)号：US11418219B2

    公开(公告)日：2022-08-16

    申请号：US17005270

    申请日：2020-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Ryota Yoshizawa ,  Kenichiro Furuta ,  Yuma Yoshinaga ,  Osamu Torii ,  Tomoya Kodama

    IPC: H03M13/29 ,  G06N3/08 ,  H03M13/45

    Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.

    Memory system
    5.
    发明授权
    Memory system 有权

    公开(公告)号：US11347584B2

    公开(公告)日：2022-05-31

    申请号：US16807220

    申请日：2020-03-03

    Applicant: Kioxia Corporation

    Inventor： Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada ,  Ryo Yamaki ,  Osamu Torii ,  Naomi Takeda

    IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16 ,  G06F3/06 ,  G06F9/30

    Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

    Memory system
    7.
    发明授权
    Memory system 有权

    公开(公告)号：US11567830B2

    公开(公告)日：2023-01-31

    申请号：US17184166

    申请日：2021-02-24

    Applicant: Kioxia Corporation

    Inventor： Yuma Yoshinaga ,  Tomoya Kodama ,  Osamu Torii ,  Kenichiro Furuta ,  Ryota Yoshizawa

    IPC: G11C29/00 ,  G06F11/10 ,  G06N3/08 ,  G06N3/04 ,  H03M13/45

    Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.

    Semiconductor memory device to hold 5-bits of data per memory cell
    8.
    发明授权
    Semiconductor memory device to hold 5-bits of data per memory cell 有权

    公开(公告)号：US11361820B2

    公开(公告)日：2022-06-14

    申请号：US17143530

    申请日：2021-01-07

    Applicant: KIOXIA CORPORATION

    Inventor： Tomonori Takahashi ,  Masanobu Shirakawa ,  Osamu Torii ,  Marie Takada

    IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

    INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
    9.
    发明申请
    INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD 有权

    公开(公告)号：US20250077572A1

    公开(公告)日：2025-03-06

    申请号：US18820977

    申请日：2024-08-30

    Applicant: Kioxia Corporation

    Inventor： Yuchieh Lin ,  Yuji Nozawa ,  youyang NG ,  Takeshi Fujiwara ,  Osamu Torii

    IPC: G06F16/583 ,  G06F16/538 ,  G06V10/44 ,  G06V10/74 ,  G06V10/82

    Abstract: An information processing apparatus includes a first neural network that extracts a feature of a query image and features of search object images; a processing circuitry detects a degree of similarity between the search object images and a query image based on the feature of the query image and the features of the search object images, and calculates a score of each of the search object images based on the degree of similarity between each of the search object images and the query image and feature transformation information relating to the degree of similarity between each of the search object images and the query image; a second neural network that outputs the feature transformation information; and a user interface that determines by a user the feature transformation information of each of the search object images based on the degree of similarity or the scores of the search object images.

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