公开(公告)号：US11610630B2

公开(公告)日：2023-03-21

申请号：US17204572

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC: G11C16/04 ,  H01L27/11519 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

公开(公告)号：US11302398B2

公开(公告)日：2022-04-12

申请号：US17023825

申请日：2020-09-17

Applicant: KIOXIA CORPORATION

Inventor： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/26 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/10

Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

公开(公告)号：US12237014B2

公开(公告)日：2025-02-25

申请号：US18171540

申请日：2023-02-20

Applicant: KIOXIA CORPORATION

Inventor： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

公开(公告)号：US11881465B2

公开(公告)日：2024-01-23

申请号：US17183809

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Nobuaki Okada ,  Toshiki Hisada

IPC: G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  G11C16/08 ,  H10B41/27 ,  H10B43/27 ,  G11C16/24

CPC classification number: H01L24/08 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction.