公开(公告)号：US20240321367A1

公开(公告)日：2024-09-26

申请号：US18599848

申请日：2024-03-08

Applicant: Kioxia Corporation

Inventor： Yoshikazu HARADA

IPC: G11C16/34 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/3404

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a transistor, an interconnect, and a first circuit. The first circuit performs an erase operation including an erase voltage applying operation of applying an erase voltage between a gate of the transistor and a channel of the transistor via the interconnect, and an erase verify operation of determining a threshold voltage of the memory cell. The first circuit performs a first suspension processing of suspending the erase operation upon receiving a first command during the erase operation. The first circuit performs the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing, based on a voltage value of the interconnect at the time of receiving the first command.

公开(公告)号：US20230021244A1

公开(公告)日：2023-01-19

申请号：US17681662

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu HARADA

IPC: G11C16/26

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, a word line connected to a gate of each of the memory cell transistors, a sequencer configured to control an operation of the memory cell array, and an input/output circuit. When the input/output circuit receives a command instructing an operation of continuously reading data of a plurality of pages from the memory cell transistors, the sequencer determines the data of the plurality of pages by continuously applying read voltages corresponding to the plurality of pages to be read, to the word line. In each continuous time period during which the control circuit applies read voltages for determining the data of one of the pages to the word line, the control circuit does not apply any read voltage for determining the data of another one of the pages to the word line.

公开(公告)号：US20230019345A1

公开(公告)日：2023-01-19

申请号：US17952402

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Yoshikazu HARADA

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10

Abstract: A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.

公开(公告)号：US20220351760A1

公开(公告)日：2022-11-03

申请号：US17864515

申请日：2022-07-14

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/02

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20210065823A1

公开(公告)日：2021-03-04

申请号：US16806684

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Masato ENDO ,  Daisuke ARIZONO ,  Yoshikazu HARADA

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  G11C16/12 ,  G11C16/04

Abstract: A semiconductor memory device includes a memory transistor, a word line, a peripheral circuit, and electrodes connected to the peripheral circuit. In response to a write command via the electrodes, the peripheral circuit can execute a first program operation of applying a first program voltage to the word line one time when the write command is one of an n1-th write command to an n2-th write command corresponding to the memory transistor; and execute a second program operation of applying a second program voltage to the first word line at least one time when the write command is one of an (n2+1)-th write command to an n3-th write command corresponding to the memory transistor. The second program voltage in a k-th second program operation is less than the first program voltage in a k-th first program operation.

公开(公告)号：US20210035646A1

公开(公告)日：2021-02-04

申请号：US16804019

申请日：2020-02-28

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu HARADA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to suspend a first operation on the memory cell array while the first operation is being performed, to start a first read operation on the memory cell array, and to resume the suspended first operation at least after the first read operation has been started. Upon receipt of a first command, a setting as to whether or not to resume the suspended first operation in response to receipt of a second command is switched. The second command is different from the first command.

公开(公告)号：US20250087263A1

公开(公告)日：2025-03-13

申请号：US18956073

申请日：2024-11-22

Applicant: Kioxia Corporation

Inventor： Manabu SATO ,  Yoshikazu HARADA ,  Naoya SHIMMYO

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

Abstract: A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.

公开(公告)号：US20240402947A1

公开(公告)日：2024-12-05

申请号：US18799669

申请日：2024-08-09

Applicant: Kioxia Corporation

Inventor： Yoshikazu HARADA

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.

公开(公告)号：US20230092551A1

公开(公告)日：2023-03-23

申请号：US17806630

申请日：2022-06-13

Applicant: Kioxia Corporation

Inventor： Manabu SATO ,  Yoshikazu HARADA ,  Naoya SHIMMYO

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074

Abstract: A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.

公开(公告)号：US20220084595A1

公开(公告)日：2022-03-17

申请号：US17200308

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Takuya KUSAKA ,  Daisuke ARIZONO ,  Yoshikazu HARADA

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14

Abstract: A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.