公开(公告)号：US20230296669A1

公开(公告)日：2023-09-21

申请号：US17898102

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Takuya KUSAKA ,  Hirosuke NARAI ,  Kazunori MASUDA ,  Makoto IWAI

IPC: G01R31/28 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: G01R31/2896 ,  G01R31/2853 ,  G01R31/2884 ,  H01L24/48 ,  H01L25/0657 ,  H01L23/5386 ,  H01L2224/48147 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L23/49816

Abstract: A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.

公开(公告)号：US20220262444A1

公开(公告)日：2022-08-18

申请号：US17463693

申请日：2021-09-01

Applicant: Kioxia Corporation

Inventor： Ryota HIRAI ,  Daisuke ARIZONO ,  Yasuhiro SHIINO ,  Takuya KUSAKA

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C16/32

Abstract: A non-volatile memory of an embodiment includes: a memory cell array including a plurality of memory cell transistors; a plurality of word lines connected to a plurality of gates of the plurality of respective memory cell transistors; a VPGM monitor connected to at least one of the plurality of word lines; and a sequencer. When writing voltage is applied to a selected word line selected from among the plurality of word lines at data writing to the memory cell array, the sequencer detects voltage of the selected word line through the VPGM monitor and determines whether detected voltage obtained through the detection has reached a predetermined value.

公开(公告)号：US20220084595A1

公开(公告)日：2022-03-17

申请号：US17200308

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Takuya KUSAKA ,  Daisuke ARIZONO ,  Yoshikazu HARADA

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14

Abstract: A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.