公开(公告)号：US4964969A

公开(公告)日：1990-10-23

申请号：US405432

申请日：1989-09-11

申请人： Kenji Kusakabe ,  Keiji Yamauchi

发明人： Kenji Kusakabe ,  Keiji Yamauchi

IPC分类号： B23K35/26 ,  C23C14/34 ,  H01L21/285 ,  H01L21/31

CPC分类号： C23C14/3407 ,  B23K35/266

摘要： A semiconductor production apparatus employs a target prepared by using a solder alloy which has a limited Sn content. The solder alloy can form an alloy layer having large elongation between a metal target and a backing plate to prevent undesirable cracking and separation of target, whereby a semiconductor device can be produced with a high degree of reliability.

摘要翻译： 半导体制造装置采用通过使用Sn含量有限的焊料合金制备的靶。 焊料合金可以形成在金属靶和背板之间具有大的伸长率的合金层，以防止不期望的目标物的开裂和分离，从而可以高度可靠地制造半导体器件。

公开(公告)号：US5374842A

公开(公告)日：1994-12-20

申请号：US20080

申请日：1993-02-19

申请人： Kenji Kusakabe

发明人： Kenji Kusakabe

IPC分类号： H01L21/322

CPC分类号： H01L21/3221 ,  Y10S257/913 ,  Y10S438/974

摘要： Silicon substrate is provided with silicon single-crystalline wafer, natural oxide film and poly-crystalline silicon film. The thickness of natural oxide film is controlled to be less than 10 .ANG.. Since the thickness of natural oxide film is made less than 10 .ANG., heavy metals travel smoothly from silicon single-crystalline wafer to poly-crystalline silicon film in the process of gettering. In other words, it is possible to enhance gettering effect.

摘要翻译： 硅衬底设置有硅单晶晶片，天然氧化物膜和多晶硅膜。 天然氧化膜的厚度控制在10安培以下。 由于天然氧化膜的厚度小于10安培，因此在吸杂过程中，重金属从硅单晶晶片平滑地移动到多晶硅膜。 换句话说，可以增强吸气效果。

公开(公告)号：US4876224A

公开(公告)日：1989-10-24

申请号：US213495

申请日：1988-06-30

申请人： Kenji Kusakabe

发明人： Kenji Kusakabe

IPC分类号： H01L21/304 ,  H01L21/02 ,  H01L21/205 ,  H01L21/306 ,  H01L21/68

CPC分类号： H01L21/68 ,  Y10S148/125

摘要： A silicon wafer for a semiconductor substrate comprises a flat wafer body, with a polycrystalline silicon layer formed only on the rear surface of said wafer body.The silicon wafer is manufactured by the steps of forming a polycrystalline silicon layer on the entire surface of the silicon wafer body, etching and removing the portion of the polycrystalline silicon layer which is formed on the side surface of silicon wafer body, and polishing and removing the polycrystalline silicon layer on the front surface of the silicon wafer body.

摘要翻译： 用于半导体衬底的硅晶片包括平坦晶片体，其中仅在所述晶片体的后表面上形成多晶硅层。 硅晶片通过以下步骤制造：在硅晶片本体的整个表面上形成多晶硅层，蚀刻并除去形成在硅晶片主体的侧表面上的多晶硅层的部分，以及抛光和去除 在硅晶片体的前表面上的多晶硅层。

公开(公告)号：US20050200547A1

公开(公告)日：2005-09-15

申请号：US10916470

申请日：2004-08-12

申请人： Izuru Naito ,  Kenji Kusakabe ,  Toshiyuki Horie ,  Syuji Nuimura

发明人： Izuru Naito ,  Kenji Kusakabe ,  Toshiyuki Horie ,  Syuji Nuimura

IPC分类号： H01Q19/19 ,  H01Q13/00

CPC分类号： H01Q1/52 ,  H01Q19/19

摘要： In order to lessen the deterioration of the VSWR, a plural-reflector antenna system is provided wherein an appropriately shaped vertex matching plate is disposed on the subreflector and electric waves that reenter the primary radiator are cancelled out. The electric waves radiated from the primary radiator are reflected by the subreflector and are radiated into space after being reflected by the main reflector. The passing area in the horn aperture, through which the reflected waves from the vertex matching plate pass, is made to be analogous to the aperture of the primary radiator, by defining the vertex matching plate as an ellipsoid, and by orienting its minor-axis direction in the major-axis direction of the main reflector and its major-axis direction, in the minor-axis direction of the main reflector.

摘要翻译： 为了减轻VSWR的劣化，提供了一种多反射器天线系统，其中适当形状的顶点匹配板设置在副反射器上，并且抵消重新进入初级辐射器的电波。 从主辐射器辐射的电波被副反射器反射，并在被主反射器反射之后被辐射到空间中。 通过将顶点匹配板定义为椭圆体，来自顶点匹配板的反射波通过的喇叭孔中的通过区域与初级辐射体的孔径类似，并且通过使其短轴 在主反射体的短轴方向上的主反射体的长轴方向及其长轴方向。

公开(公告)号：US5381032A

公开(公告)日：1995-01-10

申请号：US111964

申请日：1993-08-26

申请人： Yoshiko Kokawa ,  Tohru Koyama ,  Kenji Kusakabe ,  Katsuhiko Tamura ,  Yasuna Nakamura

发明人： Yoshiko Kokawa ,  Tohru Koyama ,  Kenji Kusakabe ,  Katsuhiko Tamura ,  Yasuna Nakamura

IPC分类号： H01L21/205 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/04

CPC分类号： H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4916

摘要： A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.

摘要翻译： 即使在通过使用栅电极作为掩模的离子注入来自对准地形成杂质区域的情况下，晶体管也不会发生误操作和特性劣化的半导体器件及其制造方法。 该半导体器件包括由具有以确定取向排列的晶粒的晶体取向的多晶硅层4b形成的栅电极。 通过使用栅极电极作为掩模通过离子注入形成p +杂质区域5时，相对于多晶硅层4b的晶粒的结晶轴以预定的角度注入离子，其中离子通过 防止栅电极。 因此，通过使用栅电极作为掩模，通过离子注入形成自对准中的杂质区域，防止了晶体管中错误操作的产生和特性劣化。

公开(公告)号：US5419786A

公开(公告)日：1995-05-30

申请号：US210398

申请日：1994-03-18

申请人： Yoshiko Kokawa ,  Kenji Kusakabe

发明人： Yoshiko Kokawa ,  Kenji Kusakabe

IPC分类号： C30B15/00 ,  C30B15/20 ,  C30B29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/322 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/306

CPC分类号： H01L21/3221 ,  H01L21/3225

摘要： A semiconductor substrate allowing reduction of crystal defects in a device formation region of an epitaxial silicon layer and allowing control of the amount of internal precipitation defects of the single crystal silicon substrate, a method of manufacturing such semiconductor substrate, and a semiconductor device utilizing such semiconductor substrate are disclosed. The semiconductor substrate includes a single crystal silicon substrate, an epitaxial silicon layer, and a polycrystalline silicon layer. The interstitial oxygen concentration of the single crystal silicon substrate is set within the range of 12.5-14.0.times.10.sup.17 (atoms/cm3) according to the old ASTM specification. The epitaxial silicon layer is formed on the top surface of the single crystal silicon substrate. The polycrystalline silicon layer is formed at least on the rear surface of the single crystal silicon substrate to a thickness of at least 1 .mu.m.

摘要翻译： 能够减少外延硅层的器件形成区域的晶体缺陷并能够控制单晶硅衬底的内部析出缺陷的量的半导体衬底，制造这种半导体衬底的方法以及利用这种半导体衬底的半导体器件 衬底。 半导体衬底包括单晶硅衬底，外延硅层和多晶硅层。 根据旧的ASTM规范，单晶硅衬底的间隙氧浓度设定在12.5-14.0×10 17（原子/ cm 3）的范围内。 外延硅层形成在单晶硅衬底的顶表面上。 多晶硅层至少形成在单晶硅衬底的后表面上至少1μm的厚度。

公开(公告)号：US5221630A

公开(公告)日：1993-06-22

申请号：US961972

申请日：1992-10-16

申请人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

发明人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/4925 ,  Y10S438/945

摘要： A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.

摘要翻译： 即使当通过使用栅极电极作为掩模的离子注入形成杂质区域时，半导体器件也不会加剧晶体管特性及其制造方法。 该半导体器件包括：由多晶硅层4形成的栅电极10，该多晶硅层4具有以预定方向排列的晶粒的晶体取向，以及形成在多晶硅层4上的单晶硅层5，晶体取向与 在多晶硅层4的沟道化现象中，通过离子注入形成杂质区6，可以防止B +离子通过到栅电极10下方的沟道现象，从而获得不具有形成晶体管特性的半导体器件加重 。

公开(公告)号：US5177569A

公开(公告)日：1993-01-05

申请号：US789722

申请日：1991-11-08

申请人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

发明人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/4925

摘要： A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.

摘要翻译： 即使当通过使用栅极电极作为掩模的离子注入形成杂质区域时，半导体器件也不会加剧晶体管特性及其制造方法。 该半导体器件包括：由多晶硅层4形成的栅电极10，该多晶硅层4具有以预定方向排列的晶粒的晶体取向，以及形成在多晶硅层4上的单晶硅层5，晶体取向与 在多晶硅层4的沟道化现象中，通过离子注入形成杂质区6，可以防止B +离子通过到栅电极10下方的沟道现象，从而获得不具有形成晶体管特性的半导体器件加重 。

公开(公告)号：US07081863B2

公开(公告)日：2006-07-25

申请号：US10526220

申请日：2003-12-25

申请人： Yoshio Inasawa ,  Shinji Kuroda ,  Yoshihiko Konishi ,  Shigeru Makino ,  Kenji Kusakabe ,  Izuru Naito

发明人： Yoshio Inasawa ,  Shinji Kuroda ,  Yoshihiko Konishi ,  Shigeru Makino ,  Kenji Kusakabe ,  Izuru Naito

IPC分类号： H01Q13/00

CPC分类号： H01Q19/19

摘要： A reflector antenna device includes: an auxiliary reflector 1 that receives an electric wave radiated from an opening portion by a primary radiator 3 and reflects the electric wave; and a main reflector 2 that receives the electric wave that is reflected by the auxiliary reflector 1 and radiates the electric wave to a space. In the reflector antenna device, the configurations of the auxiliary reflector 1 and the main reflector 2 are designed such that an electric power in an area of the main reflector 2 where the auxiliary reflector 1 is projected on the main reflector 2 in parallel with the radiating direction of the electric wave due to the main reflector 2 is equal 1 or lower than a predetermined first threshold value, and a radiation pattern of the antenna which is determined by the area of the main reflector 2 other than the area has a desired characteristic.

摘要翻译： 反射器天线装置包括：辅助反射器1，其接收由初级辐射器3从开口部分辐射的电波并反射电波; 以及主反射器2，其接收由辅助反射器1反射的电波并将电波辐射到空间。 在反射器天线装置中，辅助反射器1和主反射器2的构造被设计成使得主反射器2的辅助反射体1的区域中的电力与辅助反射体2平行地投射在主反射体2上 由于主反射器2引起的电波的方向等于1或低于预定的第一阈值，并且由除了该区域之外的主反射器2的面积确定的天线的辐射图案具有期望的特性。

公开(公告)号：US07009574B2

公开(公告)日：2006-03-07

申请号：US10916470

申请日：2004-08-12

申请人： Izuru Naito ,  Kenji Kusakabe ,  Toshiyuki Horie ,  Syuji Nuimura

发明人： Izuru Naito ,  Kenji Kusakabe ,  Toshiyuki Horie ,  Syuji Nuimura

IPC分类号： H01Q13/00

CPC分类号： H01Q1/52 ,  H01Q19/19

摘要： In order to lessen the deterioration of the VSWR, a plural-reflector antenna system is provided wherein an appropriately shaped vertex matching plate is disposed on the subreflector and electric waves that reenter the primary radiator are cancelled out.The electric waves radiated from the primary radiator are reflected by the subreflector and are radiated into space after being reflected by the main reflector. The passing area in the horn aperture, through which the reflected waves from the vertex matching plate pass, is made to be analogous to the aperture of the primary radiator, by defining the vertex matching plate as an ellipsoid, and by orienting its minor-axis direction in the major-axis direction of the main reflector and its major-axis direction, in the minor-axis direction of the main reflector.

摘要翻译： 为了减轻VSWR的劣化，提供了一种多反射器天线系统，其中适当形状的顶点匹配板设置在副反射器上，并且抵消重新进入初级辐射器的电波。 从主辐射器辐射的电波被副反射器反射，并在被主反射器反射之后被辐射到空间中。 通过将顶点匹配板定义为椭圆体，来自顶点匹配板的反射波通过的喇叭孔中的通过区域与初级辐射体的孔径类似，并且通过使其短轴 在主反射体的短轴方向上的主反射体的长轴方向及其长轴方向。