公开(公告)号：US20210083069A1

公开(公告)日：2021-03-18

申请号：US16806146

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Mitsuo IKEDA ,  Daisuke IKENO ,  Akihiro KAJITA

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/11563

Abstract: According to one embodiment, a semiconductor device includes a substrate, a plurality of insulating films and a plurality of electrode films provided alternately on the substrate. The semiconductor device further includes a first insulating film, a first charge storage film, a third insulating film, a second charge storage film, a second insulating film, and a first semiconductor film that are sequentially provided along at least one side surface of each of the electrode films. The first charge storage film includes either (i) molybdenum, or (ii) titanium and nitrogen, and the second charge storage film includes a semiconductor film.

公开(公告)号：US20240081073A1

公开(公告)日：2024-03-07

申请号：US18459795

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Ryosuke UMINO ,  Daisuke IKENO ,  Masayuki KITAMURA ,  Akihiro KAJITA

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A semiconductor device according to the present disclosure includes a first insulating film, a second insulating film, and a tungsten film provided between the first insulating film and the second insulating film, the tungsten film having a crystal particle, wherein a thickness T of the tungsten film in a first direction from the first insulating film toward the second insulating film and an average particle size APS of the crystal particle satisfy APS/T≤2 is satisfied.

公开(公告)号：US20230092843A1

公开(公告)日：2023-03-23

申请号：US17681357

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Mitsuo IKEDA ,  Daisuke IKENO ,  Akihiro KAJITA

IPC: H01L27/11582

Abstract: According to one embodiment, a semiconductor device includes a tunnel insulating film, a charge trap film on the tunnel insulating film, and a block insulating film on the charge trap film. The charge trap film is between the tunnel insulating film and the block insulating film. A conductive film is on the block insulating film. The block insulating film is between the charge trap film and the conductive film. The conductive film includes a first metal film adjacent to the block insulating film and a second metal film on the first metal film. The first metal film is between the block insulating film and the second metal film. The first metal film has an interfacial roughness on a side facing the second metal film that is greater than an interfacial roughness on a side facing the block insulating film.

公开(公告)号：US20220085051A1

公开(公告)日：2022-03-17

申请号：US17197241

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Daisuke IKENO ,  Akihiro KAJITA

IPC: H01L27/11578 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11565

Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating layer, a second insulating layer, the first insulating layer between the semiconductor substrate and the second insulating layer, a semiconductor layer between the first insulating layer and the second insulating layer, the semiconductor layer extending in a first direction parallel to a surface of the semiconductor substrate, a gate electrode layer extending in a direction perpendicular to the surface; a first insulating film between the semiconductor layer and the gate electrode layer, a second insulating film between the first insulating film and the gate electrode layer the second insulating film in contact with the first insulating layer and the second insulating layer, a polycrystalline silicon region between the first insulating film and the second insulating film; and a metal film between the polycrystalline silicon region and the second insulating film containing titanium and silicon.

公开(公告)号：US20210296238A1

公开(公告)日：2021-09-23

申请号：US17121899

申请日：2020-12-15

Applicant: Kioxia Corporation

Inventor： Mitsuo IKEDA ,  Daisuke IKENO ,  Akihiro KAJITA

IPC: H01L23/535 ,  H01L29/45 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a conductor including tungsten (W) or molybdenum (Mo); a first film provided between the conductor and the semiconductor substrate and including titanium (Ti) and silicon (Si); an insulating layer surrounding the conductor; and a second film provided between the conductor and the insulating layer, surrounding the conductor, and including titanium (Ti) and nitrogen (N). A first distance between the semiconductor substrate and an end portion of the second film on a side opposite to the semiconductor substrate is smaller than a second distance between the semiconductor substrate and an end portion of the conductor on a side opposite to the semiconductor substrate.

公开(公告)号：US20230413555A1

公开(公告)日：2023-12-21

申请号：US18177734

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Hiroki KITAYAMA ,  Tomotaka ARIGA ,  Mitsuo IKEDA ,  Daisuke IKENO ,  Akihiro KAJITA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: According to one embodiment, a semiconductor storage device includes a memory pillar extending in a first direction. The memory pillar includes a tunnel insulation film, a charge storage layer on the tunnel insulation film, and a first block insulation film on the charge storage layer. A conductor layer extends in a second direction intersecting the first direction to meet a portion of the memory pillar. The conductor layer includes a first layer comprising molybdenum and a second layer comprising tungsten. The first layer is between the memory pillar and the second layer in the second direction.

公开(公告)号：US20220406710A1

公开(公告)日：2022-12-22

申请号：US17682810

申请日：2022-02-28

Applicant: Kioxia Corporation

Inventor： Tatsuya NOMURA ,  Daichi NISHIKAWA ,  Daisuke IKENO ,  Akihiro KAJITA

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/3213

Abstract: A semiconductor device includes a conductive layer extending in a first direction, including a first surface, a second surface facing the first surface in a second direction intersecting the first direction, a third surface, and a fourth surface facing the third surface in a third direction intersecting the first direction and the second direction, and containing a first element which is at least one element of tungsten (W) or molybdenum (Mo); a first region disposed on a first surface side of the conductive layer, containing a second element which is at least one element of tungsten (W) or molybdenum (Mo), and a third element which is at least one element of sulfur (S), selenium (Se), or tellurium (Te), and including a first crystal; and a second region disposed on a second surface side of the conductive layer, containing the second element and the third element, and including a second crystal.

公开(公告)号：US20250089342A1

公开(公告)日：2025-03-13

申请号：US18822592

申请日：2024-09-03

Applicant: Kioxia Corporation

Inventor： Daichi NISHIKAWA ,  Daisuke IKENO ,  Junichi HAMAGUCHI ,  Yoshiki SAITO ,  Akihiro KAJITA

IPC: H01L29/49 ,  H01L21/28

Abstract: A semiconductor device of an embodiment includes: first and second regions that are provided in a substrate, the first and second regions containing impurities of a first conductivity type; a gate electrode disposed above the substrate between the first and second regions; first and second metal silicide layers disposed in the first and second regions, respectively; and first and second contacts connected to the first and second regions via the first and second metal silicide layers, respectively, in which the first and second contacts include: first and second oxidized silicide layers that are disposed at lower end portions of the first and second contacts and contain a predetermined metal different from metals included in the first and second metal silicide layers, respective; and metal layers that are in contact with the first and second oxidized silicide layers and extend in a second direction that intersects the first direction, respectively.

公开(公告)号：US20240097044A1

公开(公告)日：2024-03-21

申请号：US18456419

申请日：2023-08-25

Applicant: Kioxia Corporation

Inventor： Yusuke KASAHARA ,  Kappei IMAMURA ,  Akifumi GAWASE ,  Shinji MORI ,  Akihiro KAJITA

IPC: H01L29/786 ,  H01L29/417 ,  H10B12/00

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/78642 ,  H01L29/7869 ,  H10B12/05 ,  H10B12/33

Abstract: According to one embodiment, a semiconductor device includes a first conductive layer between first and second insulating layers with an oxide semiconductor column extending in the first direction through these layers. A third insulating layer covers the column. The column has a first semiconductor portion at a first position matching the first insulating layer, a second semiconductor portion at a second position matching second insulating layer, and a third semiconductor portion at a third position matching the first conductive layer. The first semiconductor portion is continuous along a second direction between the third insulating layer, the second semiconductor portion is continuous along the second direction between the third insulating layer, but the third semiconductor portion is not continuous between the third insulating layer.

公开(公告)号：US20230046783A1

公开(公告)日：2023-02-16

申请号：US17550062

申请日：2021-12-14

Applicant: Kioxia Corporation

Inventor： Hiroki KITAYAMA ,  Mitsuo IKEDA ,  Daisuke IKENO ,  Akihiro KAJITA

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first insulating layer, a first conductive layer, a first pillar, a second pillar, and a second insulating layer. The first conductive layer contains tungsten. The first conductive layer includes a first sub conductive layer and a second sub conductive layer. The first pillar and the second pillar pass through the first insulating layer and the first conductive layer. The second insulating layer divides the first insulating layer and the first conductive layer. The first sub conductive layer is in contact with the second sub conductive layer and is provided between the second sub conductive layer and the first insulating layer. A fluorine concentration in the first sub conductive layer is lower than that in the second sub conductive layer.