利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.035 秒)

    Chip Stacking Device Having Re-Distribution Layer
    1.
    发明申请
    Chip Stacking Device Having Re-Distribution Layer 审中-公开
    具有再分配层的芯片堆叠装置

    公开(公告)号：US20110062590A1

    公开(公告)日：2011-03-17

    申请号：US12832776

    申请日：2010-07-08

    申请人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    发明人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    IPC分类号： H01L23/482

    CPC分类号： H01L23/525 ,  H01L23/3171 ,  H01L23/4828 ,  H01L23/5328 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

    摘要： A chip stacking device uses nano particle silver paste for re-distribution interconnection to form a structure having low resistance through trench filling or printing. Thus, due to its low resistance, it can effectively reduce the electrical instability due to voltage drop after current flows. Furthermore, power consumption is reduced too, with energy saved. With its stable electrical signal, its utilization scope can be further expanded to high frequency product.

    摘要翻译： 芯片堆叠装置使用纳米颗粒银浆进行再分配互连，以通过沟槽填充或印刷形成具有低电阻的结构。 因此，由于其低电阻，可以有效地降低电流流动后由于电压降引起的电不稳定性。 而且，节省能源也减少了功耗。 凭借其稳定的电气信号，其利用范围可以进一步扩大到高频产品。

    Flash memory
    2.
    发明授权
    Flash memory 有权
    闪存

    公开(公告)号：US08184464B2

    公开(公告)日：2012-05-22

    申请号：US12780109

    申请日：2010-05-14

    申请人： Kuei-Wu Chu ,  Jimmy Liang ,  Leo Lu

    发明人： Kuei-Wu Chu ,  Jimmy Liang ,  Leo Lu

    IPC分类号： G11C5/06

    CPC分类号： H01L23/48 ,  H01L24/06 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014

    摘要： A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired.

    摘要翻译： 闪存包括控制器单元和管芯。 模具连接到控制器单元。 每个模具包括上表面和下表面。 每个管芯包括至少一个电源焊盘，至少一个接地焊盘，至少一个输入/输出焊盘，选择焊盘和在上表面和下表面中的每一个上的备用/忙碌焊盘。 电源板连接到控制器单元。 接地垫并联连接到电源板。 输入/输出焊盘并联连接到接地焊盘。 选择焊盘连接到控制器单元并且用如果需要切割的导线彼此连接。 备用/繁忙焊盘连接到控制器单元，并使用可以切割的电线相互连接，如果需要的话。

    Integrated Circuit
    3.
    发明申请
    Integrated Circuit 审中-公开
    集成电路

    公开(公告)号：US20110108983A1

    公开(公告)日：2011-05-12

    申请号：US12832765

    申请日：2010-07-08

    申请人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    发明人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    IPC分类号： H01L23/498

    CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/11334 ,  H01L2924/0002 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

    摘要： An integrated circuit includes a die including contacts formed thereon. A first dielectric layer is formed on the die. The first dielectric layer includes apertures defined therein corresponding to the contacts. A second dielectric layer is formed on the second dielectric layer. The second dielectric layer includes apertures defined therein corresponding to the apertures of the first dielectric layer. Redistribution layers are located in the apertures of the first and second dielectric layers and connected to the contacts. A passivation layer is located on the second dielectric layer and the redistribution layers. The passivation layer includes apertures corresponding to the redistribution layers. A solder ball is located in each of the apertures of the passivation layer and connected to a related one of the redistribution layers.

    摘要翻译： 集成电路包括其上形成有触点的模具。 在模具上形成第一电介质层。 第一电介质层包括对应于触点的限定在其中的孔。 第二电介质层形成在第二电介质层上。 第二电介质层包括与第一介电层的孔对应的孔。 再分布层位于第一和第二电介质层的孔中并连接到触点。 钝化层位于第二介电层和再分配层上。 钝化层包括对应于再分布层的孔。 焊球位于钝化层的每个孔中并连接到相关的再分布层之一。

    Easily Stackable Dies
    4.
    发明申请
    Easily Stackable Dies 有权
    容易堆叠的模具

    公开(公告)号：US20110023574A1

    公开(公告)日：2011-02-03

    申请号：US12796101

    申请日：2010-06-08

    申请人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    发明人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    IPC分类号： B21C3/16

    CPC分类号： H01L25/0657 ,  H01L22/34 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A die includes upper contacts, lower contacts and conductive elements. The upper contacts are formed on an upper face of the die. The upper contacts include a non-connected upper contact and connected upper contacts. The lower contacts are formed on a lower face of the die. The lower contacts include a non-connected lower contact and connected lower contacts. Each of the conductive elements connects a related one of the connected upper contacts to a related one of the connected lower contacts.

    摘要翻译： 模具包括上触点，下触点和导电元件。 上部触点形成在模具的上表面上。 上部触点包括一个未连接的上触点和连接的上触点。 下触点形成在模具的下表面上。 下触点包括未连接的下触点和连接的下触点。 每个导电元件将相关的一个连接的上触点连接到相连的下触点之一。

    Easily stackable dies
    5.
    发明授权
    Easily stackable dies 有权
    易于堆叠的模具

    公开(公告)号：US08424357B2

    公开(公告)日：2013-04-23

    申请号：US12796101

    申请日：2010-06-08

    申请人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    发明人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    IPC分类号： B21D37/16

    CPC分类号： H01L25/0657 ,  H01L22/34 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A die includes upper contacts, lower contacts and conductive elements. The upper contacts are formed on an upper face of the die. The upper contacts include a non-connected upper contact and connected upper contacts. The lower contacts are formed on a lower face of the die. The lower contacts include a non-connected lower contact and connected lower contacts. Each of the conductive elements connects a related one of the connected upper contacts to a related one of the connected lower contacts.

    摘要翻译： 模具包括上触点，下触点和导电元件。 上部触点形成在模具的上表面上。 上部触点包括一个未连接的上触点和连接的上触点。 下触点形成在模具的下表面上。 下触点包括未连接的下触点和连接的下触点。 每个导电元件将相关的一个连接的上触点连接到相连的下触点之一。

    Chip for Reliable Stacking on another Chip
    6.
    发明申请
    Chip for Reliable Stacking on another Chip 审中-公开
    芯片可靠堆叠在另一个芯片上

    公开(公告)号：US20110062586A1

    公开(公告)日：2011-03-17

    申请号：US12814458

    申请日：2010-06-13

    申请人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    发明人： Leo Lu ,  Kuei-Wu Chu ,  Jimmy Liang

    IPC分类号： H01L23/538

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00

    摘要： A chip includes a device, a passivation layer, two dielectric layers, at least one upper redistribution layer, at least one lower redistribution layer, at least one tunnel, at least one conductor, a redistribution passivation layer and at least one solder ball. The device includes at least one pad. The tunnel is defined in the upper redistribution layer, the first dielectric layer, the passivation layer, the pad, the device, the chip, the second dielectric layer and the lower redistribution layer. The conductor is located in the tunnel and connected to the upper and lower redistribution layers. The redistribution passivation layer is located on the second dielectric layer, the lower redistribution layer and the conductor. The solder ball is located on a portion of the lower redistribution layer through an aperture defined in the redistribution passivation layer. The chip can be connected to a printed circuit board by the solder ball.

    摘要翻译： 芯片包括器件，钝化层，两个电介质层，至少一个上再分配层，至少一个下再分配层，至少一个隧道，至少一个导体，再分布钝化层和至少一个焊球。 该装置包括至少一个垫。 隧道定义在上再分配层，第一介电层，钝化层，焊盘，器件，芯片，第二介电层和下再分布层中。 导体位于隧道内并与上，下重分布层连接。 再分布钝化层位于第二介电层，下再分布层和导体上。 焊球通过限定在再分布钝化层中的孔位于下再分布层的一部分上。 芯片可以通过焊球连接到印刷电路板。

    Flash memory
    7.
    发明申请
    Flash memory 有权
    闪存

    公开(公告)号：US20110019457A1

    公开(公告)日：2011-01-27

    申请号：US12780109

    申请日：2010-05-14

    申请人： Kuei-Wu Chu ,  Jimmy Liang ,  Leo Lu

    发明人： Kuei-Wu Chu ,  Jimmy Liang ,  Leo Lu

    IPC分类号： G11C16/04

    CPC分类号： H01L23/48 ,  H01L24/06 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014

    摘要： A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired.

    摘要翻译： 闪存包括控制器单元和管芯。 模具连接到控制器单元。 每个模具包括上表面和下表面。 每个管芯包括至少一个电源焊盘，至少一个接地焊盘，至少一个输入/输出焊盘，选择焊盘和在上表面和下表面中的每一个上的备用/忙碌焊盘。 电源板连接到控制器单元。 接地垫并联连接到电源板。 输入/输出焊盘并联连接到接地焊盘。 选择焊盘连接到控制器单元并且用如果需要切割的导线彼此连接。 备用/繁忙焊盘连接到控制器单元，并使用可以切割的电线相互连接，如果需要的话。

    Multi-Layered Circuit Board Device
    8.
    发明申请
    Multi-Layered Circuit Board Device 审中-公开
    多层电路板装置

    公开(公告)号：US20120181065A1

    公开(公告)日：2012-07-19

    申请号：US13160928

    申请日：2011-06-15

    申请人： Kuei-Wu Chu

    发明人： Kuei-Wu Chu

    IPC分类号： H05K1/09

    CPC分类号： H05K3/4644 ,  H05K3/4605 ,  H05K3/4664 ,  H05K2203/025

    摘要： A multi-layered circuit board device includes an isolative layer and a wiring layer sequentially provided on a circuit board in a PCB, ceramic, LTCC or aluminum nitride build-up process. Thus, the thickness of the multi-layered circuit board device is small and the density of the multi-layered the circuit board device is high. Furthermore, the structure of the multi-layered circuit board device is simple and the cost of the multi-layered circuit board device is low. The layers are connected to one another in the PCB, ceramic, LTCC or aluminum nitride build-up process without having to use additional alignment target points.

    摘要翻译： 多层电路板装置包括依次设置在PCB，陶瓷，LTCC或氮化铝填充工艺中的电路板上的隔离层和布线层。 因此，多层电路板装置的厚度小，并且多层电路板装置的密度高。 此外，多层电路板装置的结构简单，并且多层电路板装置的成本低。 这些层在PCB，陶瓷，LTCC或氮化铝堆积过程中彼此连接，而不必使用附加的对准目标点。