公开(公告)号：US07398801B2

公开(公告)日：2008-07-15

申请号：US11292674

申请日：2005-12-02

申请人： Kun-Hyung Lee ,  Soo-Woong Lee ,  Hyun-Ho Cho ,  Hee-Sun Chae ,  Jae-Hyung Jung ,  Sun-Yong Lee

发明人： Kun-Hyung Lee ,  Soo-Woong Lee ,  Hyun-Ho Cho ,  Hee-Sun Chae ,  Jae-Hyung Jung ,  Sun-Yong Lee

IPC分类号： B65B1/20

CPC分类号： H01L21/67017 ,  H01L21/67772 ,  Y10S414/14

摘要： An apparatus and method for manufacturing semiconductor devices are disclosed. In accordance with the invention, a wafer transfer device for transferring wafers from wafer storage containers to wafer processing equipment includes a flow chamber designed to reduce the amount of contaminants that can enter the wafer container. The wafer transfer apparatus provide two gas inlets for allowing two gases to flow through the flow chamber of the transfer apparatus. This results in a reduced amount of contaminants able to enter the wafer container, which in turn results in manufacture of devices with more reliable performance characteristics as well as high manufacturing yield.

摘要翻译： 公开了一种用于制造半导体器件的设备和方法。 根据本发明，用于将晶片从晶片储存容器转移到晶片加工设备的晶片转移装置包括设计成减少可进入晶片容器的污染物量的流动室。 晶片传送装置提供两个气体入口，用于允许两种气体流过传送装置的流动室。 这导致能够进入晶片容器的污染物量减少，这进而导致具有更可靠的性能特征以及高制造产量的装置的制造。

公开(公告)号：US20060104750A1

公开(公告)日：2006-05-18

申请号：US11292674

申请日：2005-12-02

申请人： Kun-Hyung Lee ,  Soo-Woong Lee ,  Hyun-Ho Cho ,  Hee-Sun Chae ,  Jae-Hyung Jung ,  Sun-Yong Lee

发明人： Kun-Hyung Lee ,  Soo-Woong Lee ,  Hyun-Ho Cho ,  Hee-Sun Chae ,  Jae-Hyung Jung ,  Sun-Yong Lee

IPC分类号： H01L21/677

CPC分类号： H01L21/67017 ,  H01L21/67772 ,  Y10S414/14

摘要： An apparatus and method for manufacturing semiconductor devices are disclosed. In accordance with the invention, a wafer transfer device for transferring wafers from wafer storage containers to wafer processing equipment includes a flow chamber designed to reduce the amount of contaminants that can enter the wafer container. The wafer transfer apparatus provide two gas inlets for allowing two gases to flow through the flow chamber of the transfer apparatus. This results in a reduced amount of contaminants able to enter the wafer container, which in turn results in manufacture of devices with more reliable performance characteristics as well as high manufacturing yield.

摘要翻译： 公开了一种用于制造半导体器件的设备和方法。 根据本发明，用于将晶片从晶片储存容器转移到晶片加工设备的晶片转移装置包括设计成减少可进入晶片容器的污染物量的流动室。 晶片传送装置提供两个气体入口，用于允许两种气体流过传送装置的流动室。 这导致能够进入晶片容器的污染物量减少，这进而导致具有更可靠的性能特征以及高制造产量的装置的制造。

公开(公告)号：US5828039A

公开(公告)日：1998-10-27

申请号：US774606

申请日：1996-12-30

申请人： Hee-Sun Chae

发明人： Hee-Sun Chae

IPC分类号： H01L21/306 ,  G05D23/19 ,  H01L21/304 ,  H05B1/02

CPC分类号： G05D23/1919

摘要： A method and apparatus for heating a chemical used in microelectronic device fabrication processes. The apparatus includes a chemical supply and chemical bath for containing a chemical. A temperature sensor senses the temperature of the chemical contained in the chemical bath. A first heater, powered by a first electric power source, heats the chemical while it is being supplied to the chemical bath. A second heater, powered by a second electric power source, heats the chemical contained in the chemical bath. First and second power controllers regulate the first electric power and the second electric power sources, respectively, through a plurality of electrodes having different intensity levels that are selected according to the temperature of the chemical sensed by the temperature sensor.

摘要翻译： 一种用于加热微电子器件制造工艺中使用的化学品的方法和装置。 该设备包括用于容纳化学品的化学品供应和化学浴。 温度传感器检测化学浴中含有的化学物质的温度。 由第一电源供电的第一加热器在将化学品供应给化学浴时加热。 由第二电源供电的第二加热器加热化学浴中所含的化学品。 第一和第二功率控制器分别通过根据由温度传感器感测到的化学物质的温度选择的具有不同强度水平的多个电极来分别调节第一电功率和第二电源。

公开(公告)号：US5816970A

公开(公告)日：1998-10-06

申请号：US773884

申请日：1996-12-26

申请人： Hee-Sun Chae

发明人： Hee-Sun Chae

IPC分类号： G01L5/10 ,  F16H7/22

CPC分类号： G01L5/10

摘要： The present invention relates to a semiconductor fabricating apparatus having an electrical system for transmitting a rotatory power through a belt of a motor to a pulley. The semiconductor fabricating apparatus having an electrical system of the present invention includes a sensor disposed in the vicinity of the belt for detecting a distance between the sensor and the belt and generating an electrical signal corresponding to a detected distance; an amplifier for amplifying the electrical signal to generate an amplified voltage; an analog-to-digital converter for converting the amplified voltage into a digital signal; and a controller for comparing the digital signal with a reference signal and determining whether the belt is loose on the pulley so as to generate a control signal. When the belt deviates out of the pulleys during the process, the loose belt makes the pulleys run idle, the belt cuts off, or the rotation of the motor stops, the present invention helps an operator recognize such an unexpected abrupt situation and take an appropriate action to solve the above problems at once.

摘要翻译： 本发明涉及一种具有电气系统的半导体制造装置，该电气系统通过马达的带传递旋转动力到滑轮。 具有本发明的电气系统的半导体制造装置包括设置在皮带附近的传感器，用于检测传感器和皮带之间的距离并产生对应于检测距离的电信号; 用于放大电信号以产生放大电压的放大器; 用于将放大的电压转换成数字信号的模拟 - 数字转换器; 以及控制器，用于将数字信号与参考信号进行比较，并且确定皮带是否在皮带轮上松动以产生控制信号。 当皮带在加工过程中偏离皮带轮时，松套带使皮带轮怠速运转，皮带切断或马达转动停止，本发明有助于操作者识别出这种意外的突发情况，并采取适当的 立即解决上述问题的行动。

公开(公告)号：US06766210B2

公开(公告)日：2004-07-20

申请号：US10222852

申请日：2002-08-19

申请人： Tae-Ha Jun ,  Hee-Sun Chae ,  Kyung-Bo Sim ,  Jong-Hwan Weon

发明人： Tae-Ha Jun ,  Hee-Sun Chae ,  Kyung-Bo Sim ,  Jong-Hwan Weon

IPC分类号： G06F1900

CPC分类号： G05B19/4184 ,  G05B2219/36542 ,  Y02P90/14 ,  Y02P90/18

摘要： A method for preventing process errors in a semiconductor fabricating process allows only a few authorized engineers to release interlocks of semiconductor fabricating equipment when a count of interlock occurrences exceeds a predetermined number within a predetermined period of time. By allowing a semiconductor fabricating equipment operator only limited ability to reset equipment interlocks, repeated interlock conditions caused by test specification failures may be over-ridden only a predetermined number of times before the semiconductor fabricating equipment is disabled completely. The disabled semiconductor fabricating equipment may only be re-enabled using an authorization code, which is only made available to selected personnel, thereby ensuring that necessary repairs and corrections have been implemented on the semiconductor fabricating equipment.

摘要翻译： 一种防止半导体制造工艺中的工艺误差的方法允许只有少数授权的工程师在预定的时间内互锁次数超过预定数量时才能释放半导体制造设备的互锁。 通过允许半导体制造设备操作者仅限于重置设备互锁的能力，在半导体制造设备完全禁用之前，由测试规范故障引起的重复互锁条件可能会超过预定次数。 禁用的半导体制造设备只能使用授权码重新启用，该授权码仅对选定的人员可用，从而确保在半导体制造设备上已经实施了必要的修理和更正。

公开(公告)号：US06604012B1

公开(公告)日：2003-08-05

申请号：US09644294

申请日：2000-08-23

申请人： Dae-Sik Cho ,  Hee-Sun Chae ,  Seok-Hyun Kim ,  Seung-Hoon Tong ,  Tae-Yang Yoon ,  Doh-Soon Kwak ,  Hee-Se Kang ,  Yll-Seug Park ,  Jae-Seok Oh

发明人： Dae-Sik Cho ,  Hee-Sun Chae ,  Seok-Hyun Kim ,  Seung-Hoon Tong ,  Tae-Yang Yoon ,  Doh-Soon Kwak ,  Hee-Se Kang ,  Yll-Seug Park ,  Jae-Seok Oh

IPC分类号： G06F1900

CPC分类号： G05B19/41875 ,  G05B2219/32077 ,  G05B2219/32198 ,  G05B2219/32263 ,  G05B2219/45031 ,  Y02P90/12 ,  Y02P90/20 ,  Y02P90/22

摘要： A lot dispatching method and system for variably applying the most suitable processing equipment and/or processing condition in a succeeding process of a semiconductor manufacturing process, wherein the succeeding process is influenced by the result of a preceding process. A lot processed by the preceding process is dispatched to the succeeding processing equipment according to a systematic analysis result obtained from a relationship between a process result of the preceding process and an efficiency and the characteristics of a plurality of processing equipment in the succeeding process. A plurality of process conditions for the succeeding process corresponding to the performance of the preceding process is provided. A respective process condition has characteristics that minimize the difference in performance in the succeeding process from a desired or target performance. By systematically analyzing the quality of the lot waiting to be dispatched, the succeeding process is performed with the most suitable process condition.

摘要翻译： 用于在半导体制造过程的后续过程中可变地应用最合适的处理设备和/或处理条件的大量调度方法和系统，其中后续处理受到前一处理的结果的影响。 根据从前一处理的处理结果与效率之间的关系获得的系统分析结果和后续处理中的多个处理设备的特性，将由前述处理进行的许多处理分派到后续处理设备。 提供了与前述处理的执行相对应的用于后续处理的多个处理条件。 相应的处理条件具有使从后续处理中的性能与期望性能或目标性能的差异最小化的特征。 通过系统地分析等待发送的批次的质量，以最合适的处理条件进行后续处理。

公开(公告)号：US6027604A

公开(公告)日：2000-02-22

申请号：US73250

申请日：1998-05-06

申请人： Joung-hyun Lim ,  Hee-Sun Chae

发明人： Joung-hyun Lim ,  Hee-Sun Chae

IPC分类号： C23F4/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  B08B7/00

CPC分类号： H01L21/67069

摘要： A dry etching apparatus is capable of suppressing formation of reaction products (i.e., polymers) in an etching chamber. A gas supply is connected to the top of the etching chamber by a first gas duct, and a pump is connected to the bottom of the etching chamber by a second gas duct. An upper electrode is furnished in the etching chamber. At a location opposed to the upper electrode, a lower electrode is furnished. Insulation plates of the upper and the lower electrodes, or an insulation plate of either of the upper or the lower electrode, include a plurality of grooves. The etching chamber may include a plurality of grooves and projections on its sidewalls. The plurality of projections in the sidewalls has a semicircular or a rectangular cross-section, and may be formed as a single body or as individually detachable projection bodies. Accordingly, it is possible to improve the conductance and exhaustion velocity in the etching chamber using the plurality of grooves in the insulation plates of the electrodes and the grooves in the sidewalls of the chamber. As a result, the formation of polymers that may act as particles during an etching process can be suppressed. Additionally, the accumulated polymers can be more widely dispersed.

摘要翻译： 干蚀刻装置能够抑制蚀刻室中的反应产物（即聚合物）的形成。 气体供应通过第一气体管道连接到蚀刻室的顶部，并且泵通过第二气体管道连接到蚀刻室的底部。 在蚀刻室中设置有上电极。 在与上电极相对的位置处，设置有下电极。 上电极和下电极的绝缘板或上电极或下电极中的任一个的绝缘板包括多个槽。 蚀刻室可以在其侧壁上包括多个凹槽和凸起。 侧壁中的多个突起具有半圆形或矩形横截面，并且可以形成为单个主体或单独可拆卸的突出体。 因此，可以使用电极的绝缘板中的多个槽和腔室的侧壁中的槽来提高蚀刻室中的导电和排出速度。 结果，可以抑制在蚀刻过程中可能作为颗粒的聚合物的形成。 此外，聚合的聚合物可以更广泛地分散。

公开(公告)号：US07598180B2

公开(公告)日：2009-10-06

申请号：US11458553

申请日：2006-07-19

申请人： Jeong-Hun Park ,  Hee-Sun Chae ,  Kyoung-Shin Park

发明人： Jeong-Hun Park ,  Hee-Sun Chae ,  Kyoung-Shin Park

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L27/10894 ,  H01L27/10897 ,  H01L28/90

摘要： A method for removing defects due to edge chips of a semiconductor wafer is disclosed. This method includes forming a molding layer over a semiconductor wafer. The molding layer is patterned to form a plurality of storage node holes, where the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area. First storage nodes and second storage nodes are formed in the first and second storage node holes, respectively. A photoresist pattern is formed on the wafer having the storage nodes. The photoresist pattern is preferably formed to expose the effective chip areas and to cover the edge chip areas. The molding layer is etched, using the photoresist pattern as an etching mask, to expose portions of the first storage nodes.

摘要翻译： 公开了一种用于消除由半导体晶片的边缘芯片引起的缺陷的方法。 该方法包括在半导体晶片上形成模塑层。 模塑层被图案化以形成多个存储节点孔，其中多个存储节点孔包括形成在有效芯片区域上的至少一个第一存储节点孔和形成在边缘芯片区域上的至少一个第二存储节点孔。 第一存储节点和第二存储节点分别形成在第一和第二存储节点孔中。 在具有存储节点的晶片上形成光致抗蚀剂图案。 光致抗蚀剂图案优选地形成为暴露有效芯片区域并覆盖边缘芯片区域。 使用光致抗蚀剂图案作为蚀刻掩模蚀刻成型层，以露出第一存储节点的部分。

公开(公告)号：US07101752B2

公开(公告)日：2006-09-05

申请号：US10809076

申请日：2004-03-24

申请人： Jeong-Hun Park ,  Hee-Sun Chae ,  Kyoung-Shin Park

发明人： Jeong-Hun Park ,  Hee-Sun Chae ,  Kyoung-Shin Park

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10897 ,  H01L28/90

摘要： A method for removing defects due to edge chips of a semiconductor wafer is disclosed. This method includes forming a molding layer over a semiconductor wafer. The molding layer is patterned to form a plurality of storage node holes, where the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area. First storage nodes and second storage nodes are formed in the first and second storage node holes, respectively. A photoresist pattern is formed on the wafer having the storage nodes. The photoresist pattern is preferably formed to expose the effective chip areas and to cover the edge chip areas. The molding layer is etched, using the photoresist pattern as an etching mask, to expose portions of the first storage nodes.